Thumb Instruction Set

Introduction
Thumb has higher performance than
ARM on a processor with a 16-bit
data bus
Thumb has higher code density than
ARM
Thumb implementation takes up
around 30% less memory than the
equivalent ARM implementation
ASR, LSL, LSR, and ROR used as
separate instructions in the Thumb

Thumb Register Usage

Only the low registers r0 to r7 are fully
accessible
higher registers r8 to r12 are only
accessible with MOV, ADD, or CMP
instructions
CMP and all the data processing
instructions that operate on low registers
update the condition flags in the cpsr
no coprocessor instructions available in
Thumb state

ARM-Thumb Interworking
ARM-Thumb interworking is the
method of linking ARM and Thumb
code together for both assembly and
C/C++
To call a Thumb routine from an ARM
routine, the core has to change state
BX and BLX branch instructions cause
a switch between ARM and Thumb
state

 BX and BLX ARM instructions have a

associated Thumb equivalent
ARM BX instruction enters Thumb
state only if bit 0 of the address in Rn
is set to binary 1
Thumb BX instruction does the same
Thumb BX instruction cannot be
conditionally executed

Branch Instructions
B is similar to the ARM version and is
conditionally executed
branch range is limited to a signed 8bit immediate, or 256 to +254
bytes
BL instruction is not conditionally
executed and has an approximate
range of+/4 MB

Data Processing Instructions

Thumb data processing instructions
are subset of ARM data processing
instructions

Single-Register Load-Store
Thumb instruction set supports load
and storing registers
two preindexed addressing modes:
offset by register and offset by
immediate

 offset by register uses a base register

Rn plus the register offset Rm
second type uses the same base
register Rn plus a 5-bit immediate or a
value dependent on the data size
5-bit offset encoded in the instruction
is multiplied by one for byte accesses,
two for 16-bit accesses, and four for
32-bit accesses

Multiple-Register Load-Store
only support the increment after (IA)
addressing mode
always update the base register Rn
after execution

Stack Instructions
POP and PUSH instructions used for stack
operation
stack pointer is fixed as register r13 in
Thumb operations
sp is automatically updated
PUSH register list also can include the link
register lr
POP register list can include the pc
Full Descending stack alone is supported

Software Interrupt
Instruction
Thumb software interrupt (SWI) instruction
causes a software interrupt exception
If any interrupt or exception flag is raised in
Thumb state, the processor automatically
reverts back to ARM state
SWI number is limited to the range 0 to 255
Not conditionally executed

ARM Assembly
Programming

Areas
It may be CODE or DATA, and can
optionally be READONLY.
Eg. AREA |main|, CODE, READONLY
The area name must be enclosed in
vertical bars, and it may be any valid
identifier

ENTRY
For a stand-alone program ENTRY
directive tell the assembler that this
is where program start execution.
only one entry point per program.

 In assembler code, Things on the left are

counted as identifiers
while things that are indented on center are
either instructions or directives.
Any line beginning with a semicolon is a
comment
a semicolon in a line of code means that the
rest of the line is a comment.
You can only have one instruction per line.

register to the display in hexadecimal

AREA Simple,CODE,READONLY
ENTRY
MOV R1,#00000010H
MOV R2,R1
ADD R2,R0,R1,LSR #1
RSB R0,R2,R1
END

AREA Test, CODE, READONLY

EXPORT test
test
MOV r1,#0X00000004
LDR r0,[r1,#4]
ADD r1,r1,#2
MOV r0,#0x000000000A
BIC r1,r1,r0
END

AREA Test, CODE, READONLY

ENTRY
MOV r0, #0x00000001
MOV r1, #0x00000004
ADD r2, r0, r1,LSL #4
SUB r2,r1,r0
RSB r2,r0,r2
END

AREA Biggest, CODE, READONLY

ENTRY
LDR R1,Value1
LDR R2,Value2
CMP R1,R2
BHI Done
MOV R3,R2
Done
MOV R3,R1
AREA DATA
Value1 DCD &12345678
Value2 DCD &87654321
END

AREA Multiply, CODE, READONLY

ENTRY
LDR R0,=0X12345678
LDR R1,=0X87654321
UMULL R4,R5,R0,R1
SMULL R6,R7,R0,R1
END