L22-L23-Pipelining Hazards

Lecture 22 and Lecture 23
Hazards Involved in Pipelining

CSC208A-Computer Organisation and
Architecture
B. Tech. 2015
Course Leader:
PRAKASH P
prakashp.cs.et@msruas.ac.in
aculty of Engineering & Technology
1
M. S. Ramaiah University of Applied Sciences
Objectives
At the end of these lectures, students will be
able to
Differentiate the hazards that a pipeline is
susceptible to
Explain implementations of the techniques that
are used to overcome these hazards
Analyze the effect that these hazards and their
resolution, have on the performance of the
pipeline
2
Pipelining Hazards
Structural
Resource conflicts when the hardware cant support all
combinations of overlapped stages
e.g. Might use ALU to add 4 to PC and execute op
Data
An instruction depends on the results of some previous
instruction that is still being processed in the pipeline
e.g. R1 = R2 + R3; R4 = R1 + R6; problem here?
Control
Branches and other instructions that change the PC
If we branch, we may have the wrong instructions in the
pipeline
3
Structural Hazard
Overlapped execution may require duplicate
resources
Clock 4:
Memory access for i may conflict with IF for i+4
May solve via separate cache/buffer for instructions,
data
IF might use the ALU which conflicts with EX`
4
Dealing with Hazards

One solution: Stall
Let the instructions later in the stage continue,
and stall the earlier instruction
Need to do in this order, since if we stalled the later
instructions, they would become a bottleneck and
nothing else could move out of the pipeline
Once the problem is cleared, the stall is cleared

Often called a pipeline bubble since it floats
through the pipeline but does no useful work
Stalls increase the CPI from its ideal value

of 1
5
Structural Hazard Example

Consider a CPU with a single memory
pipeline for data and instructions
If an instruction contains a data memory
reference, it will conflict with the instruction
fetch
We will introduce a bubble while the latter
instruction waits for the first instruction to finish
6
7

No Instr
finished
in CC8
What if Instruction 1 is also a LOAD?
8
Alternate Depiction of A Stall
9
Avoiding Structural Hazards

How can we avoid structural hazards?
Issue of cost for the designer
E.g. allow multiple access paths to memory
Separate access to instructions from data
Build multiple ALU or other functional units

Dont forget the cost/performance tradeoff
If we dont encounter structural hazards often, it
might not be worth the expense to design
hardware to address it, instead just handle it
with a stall or other method
10
Instruction Throughput
Pipelining increases processor performance
by increasing the instruction throughput
If several instructions overlapped in the
pipeline cycle time can be reduced,
increasing the rate at which instructions
execute
11
Limiting Factors
Number of factors limit a pipeline's ability to
execute instructions at its peak rate
Dependencies between instructions operands
(called data dependency hazards)
Branches (called program flow control hazards),
and the time required to access memory
12
Instruction Pipeline Hazards
RAR
RAW
WAR
WAW
Hazard is a risk in which pipeline operations

stall (stop) for one or more clock cycles
13
Stall
The instruction at the later stage waits for
the front one to complete and thus clock
cycle(s) is not utilized during that period
Stall a bubble in the pipeline
14
Data Dependency Hazard

Can occur among the operands in the
instruction at the pipeline stages
Instruction hazards (data dependencies)
occur when instructions read or write
registers that are used by other instructions
15
Read-After-Read
Occurs when two instructions both read
from the same register
Don't cause a problem for the processor
because reading a register doesn't change
the registers value
16
Detection Condition
In an n-th instruction at an advanced
stage of processing
In+1 an n+1 th instruction at previous
stage of processing
In and In+1 contain at least one common
operand
Input operands be same in In+1 as in In
17
RAR Example
Instructions
ADD r1, r2, r3
SUB r4, r5, r3
Both instructions read r3, creating a RAR

hazard
18
Read After Write

The detection condition of RAW hazards is
that
On and In+1 contain at least one common
operand
Output operand(s) On of In
Input operands In+1 of n+1 instruction at
the back
19
RAW Example
Instructions
ADD r1, r2, r3
SUB r4, r5, r1
Subtract reads output

creating a RAW hazard
of the addition,
20
Clock Cycles
21
RAW and Pipeline Stall or Bubble

Reading instruction can proceed through
the instruction fetch and instruction decode
stages of the pipeline before the writing
instruction completes, because the reading
instruction does not need the value
produced by the writing instruction until it
reaches the register read stage
22
RAW and Pipeline Stall or Bubble

Reading instruction cannot proceed past the
register read stage of the pipeline until the
writing instruction has passed through the
write-back stage
The data that the reading instruction needs
is not available until then
Wait of a cycle pipeline stall or bubble
23
Pipeline Stall
24
Inserting NoPs
In cycle 5, the subtract would normally
enter the execute stage, but it is prevented
from doing so because it was not able to
read r1 on cycle 4
Instead, the hardware inserts a special nooperation(NOP) instruction, known as a
bubble, into the execute stage of the
pipeline, and the subtract tries to read its
input registers again on cycle 5
25
Effect of Pipeline Stalls

The result of the ADD still unavailable on
cycle 5 because the ADD has not completed
the write back stage yet,
So the subtract cannot enter the execute
stage on cycle 6
On cycle 6, the SUB is able to read r1, and it
proceeds into the execute stage on cycle 7
26
Write After Read

Hazards occur when the output register of
an instruction is used for write after read by
a previous instruction
27
Write After Write

Hazard occur when the output register of an
instruction is used for write after written by
a previous instruction
28
Effects of WAR and WAW

These hazards are sometimes called name
dependencies, as they occur because the
processor has a finite number of registers
If the processor had an infinite number of
registers, it could use a different register for
the output of each instruction, and WAW
and WAR hazards would never occur
29
WAR Detection
The detection condition of WAR hazards is
that
In and On+1 contain at least one common
operand
30
WAR Example
ADD r1, r2, r3
SUB r2, r5, r6
Subtract writes r2, which is read by the
addition, creating a WAR hazard
31
WAW Detection
The detection condition for WAW hazards is
that On and On+1 contain at least one
common operand
32
WAW Example
ADD r1, r2, r3
SUB r1, r5, r6
Subtract writes the same register as the
addition, creating a WAW hazard
33
In-Order Execution
If a processor executes instructions in the
order that they appear in the program and
uses the same pipeline for all instructions,
WAR and WAW hazards do not cause the
delays because of the way instructions
through the pipeline
34
WAW
The output register of an instruction written
in the write back stage of the pipeline
Instructions with WAW hazards will enter
the write back stage in the order in which
they appear in the program
Write their results into the register in the
right order
35
WAR
Even less of a problem, because the register read
stage of the pipeline occurs before the write back
stage
By the time an instruction enters the write back
stage of the pipeline, all previous instructions in
the program have already passed through the
register read stage and read their input values
Writing instruction can go ahead and write its
destination register without causing any problems
36
Different Latencies
WAW and WAR hazards can cause problems,
because it is possible for a low-latency
instruction to complete before a longerlatency instruction that appeared earlier in
the program
These processors must keep track of name
dependencies between instructions and
stall the pipeline as necessary to resolve
these hazards
37
WAR and WAW Hazards

An issue in out-of-order processor
Processor allows instructions to execute in
different orders than the original program to
improve performance
38
Summary
Data Dependent Hazards
RAR
RAW causes bubble
WAR and WAW results in name dependencies
WAR and WAW create the issue in out-of order
executing processor pipeline
39

L22-L23-Pipelining Hazards

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Lecture 22 and Lecture 23

Hazards Involved in Pipelining

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology

IF might use the ALU which conflicts with EX`

aculty of Engineering & Technology

Dealing with Hazards

Once the problem is cleared, the stall is cleared

Stalls increase the CPI from its ideal value

aculty of Engineering & Technology

Structural Hazard Example

aculty of Engineering & Technology

Structural Hazard Example

aculty of Engineering & Technology

Structural Hazard Example

What if Instruction 1 is also a LOAD?

aculty of Engineering & Technology

Alternate Depiction of A Stall

aculty of Engineering & Technology

Avoiding Structural Hazards

Build multiple ALU or other functional units

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology

Instruction Pipeline Hazards

Hazard is a risk in which pipeline operations

aculty of Engineering & Technology

aculty of Engineering & Technology

Data Dependency Hazard

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology

M. S. Ramaiah University of Applied Sciences

Both instructions read r3, creating a RAR

aculty of Engineering & Technology

Read After Write

aculty of Engineering & Technology

M. S. Ramaiah University of Applied Sciences

Subtract reads output

aculty of Engineering & Technology

aculty of Engineering & Technology

RAW and Pipeline Stall or Bubble

aculty of Engineering & Technology

RAW and Pipeline Stall or Bubble

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology

Effect of Pipeline Stalls

aculty of Engineering & Technology

Write After Read

aculty of Engineering & Technology

Write After Write

aculty of Engineering & Technology

Effects of WAR and WAW

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology

aculty of Engineering & Technology