Rabaey Chapter5

Digital Integrated
Circuits
Jan M. Rabaey
AAnantha
Design
Perspective
Chandrakasan
Borivoje Nikolic
The Inverter
July 30, 2002
Digital Integrated Circuits2nd
Inverter
The CMOS Inverter: A First Glance

V DD
V in
V out
CL
Inverter
CMOS Inverter
N Well
VDD
VDD
PMOS
Contacts
PMOS
In
Out
In
NMOS
Out
Metal 1
Polysilicon
NMOS
GND
Inverter
Two Inverters
Share power and ground
Abut cells
VDD
Connect in Metal
Inverter
CMOS Inverter
First-Order DC Analysis
V DD
V DD
Rp
V out
V out
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
Rn
V in 5 V DD
V in 5 0
Inverter
CMOS Inverter: Transient Response

V DD
V DD
tpHL = f(Ron.CL)
Rp
= 0.69 RonCL
V out
V out
CL
CL
Rn
V in 5 0
V in 5 V DD
(a) Low-to-high
(b) High-to-low
Inverter
Voltage Transfer
Characteristic
Inverter
PMOS Load Lines

IDn
V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp
V out
IDp
Vin=0
IDn
IDn
V in=1.5
VGSp=-1
VGSp=-2.5
V DSp
Vin = V DD+VGSp
IDn = - IDp
Vin=0
Vin=1.5
VDSp
Vout
Vout = V DD+VDSp
Inverter
CMOS Inverter Load Characteristics

ID n
PMOS
Vin = 0
Vin = 2.5
Vin = 0.5
Vin = 2
Vin = 1
Vin = 1.5
Vin = 1.5
Vin = 2
Vin = 2.5
NMOS
Vin = 1
Vin = 1.5
Vin = 1
Vin = 0.5
Vin = 0
Vout
Inverter
CMOS Inverter VTC

NMOS off
PMOS res
2.5
Vout
NMOS s at
PMOS res
1.5
NMOS sat
PMOS sat
0.5
NMOS res
PMOS sat
0 .5
1 .5
NMOS res
PMOS off
2 .5
Vin
Inverter
Switching Threshold as a function

of Transistor Ratio
1.8
1.7
1.6
1.5
1.3
V (V)
1.4
1.2
1.1
1
0.9
0.8
10
Digital Integrated Circuits
2nd
W p /W
10
n
Inverter
Determining VIH and VIL

Vout
V OH
VM
V in
V OL
V IL
V IH
A simplified approach
Inverter
Inverter Gain
0
-2
-4
gain
-6
-8
-10
-12
-14
-16
-18
0.5
Vin (V)
1.5
2.5
Inverter
Gain as a function of VDD

2.5
0.2
0.15
Vout (V)
Vout (V)
1.5
0.1
1
0.05
0.5
0
0
Gain=-1
0.5
Vin (V)
1.5
2.5
0
0
0.05
0.1
Vin (V)
0.15
0.2
Inverter
Simulated VTC
2.5
Vout (V)
1.5
0.5
0.5
Vin (V)
1.5
2.5
Inverter
Impact of Process Variations

2.5
Good PMOS
Bad NMOS
Vout(V)
1.5
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0
0.5
Vin (V)
1.5
2.5
Inverter
Propagation Delay
Inverter
CMOS Inverter Propagation Delay

Approach 1
VDD
tpHL = CL Vswing/2
Iav
Vout
Iav
CL
CL
kn VDD
Vin = V DD
Inverter
CMOS Inverter Propagation Delay

Approach 2
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
CL
Ron
ln(0.5)
Vout
1
VDD
0.5
0.36
Vin = V DD
RonCL
Inverter
CMOS Inverters
VDD
PMOS
1.2m
=2
In
Out
Metal1
Polysilicon
NMOS
GND
Inverter
Transient Response
3
2.5
tp = 0.69 CL
(Reqn+Reqp)/2
Vout(V)
1.5
1
tpHL
tpLH
0.5
0
-0.5
0
0.5
t (sec)
1.5
2.5
-10
x 10
Inverter
Design for Performance

Keep
capacitances small
Increase transistor sizes
watch out for self-loading!
Increase
VDD (????)
Inverter
Delay as a function of VDD

5.5
5
tp(normalized)
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1.2
1.4
1.6
VDD(V)
1.8
2.2
2.4
Inverter
Device Sizing
-11
3.8
x 10
(for fixed load)
3.6
3.4
tp(sec)
3.2
3
2.8
Self-loading effect:
Intrinsic capacitances
dominate
2.6
2.4
2.2
2
8
S
10
12
14
Inverter
NMOS/PMOS ratio
-11
x 10
tpHL
tpLH
tp(sec)
4.5
= Wp/Wn
tp
4
3.5
3
1
1.5
2.5
3.5
4.5
Inverter
Impact of Rise Time on Delay

0.35
tpHL(nsec)
0.3
0.25
0.2
0.15
0.2
0.4
0.6
trise (nsec)
0.8
Inverter
Inverter Sizing
Inverter
Inverter Chain
In
Out
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.
Inverter
Inverter Delay
Minimum length devices, L=0.25m
Assume that for WP = 2WN =2W
same pull-up and pull-down currents
approx. equal resistances RN = RP
approx. equal rise tpLH and fall tpHL delays
Analyze as an RC network
1
1
WP
WN
RP Runit
Runit
RN RW
Wunit
Wunit
Delay (D): tpHL = (ln 2) RNCL
Load for the next stage:
2W
tpLH = (ln 2) RPCL
C gin
W
3
Cunit
Wunit
Inverter
Inverter with Load

Delay
RW
CL
RW
Load (CL)
tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
Wunit = 1
Inverter
Inverter with Load

CP = 2Cunit
Delay
2W
W
CN = Cunit
Cint
CL
Load
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)
Inverter
Delay Formula
Delay ~ RW Cint C L
t p kRW Cint 1 C L / Cint t p 0 1 f /
Cint = Cgin with 1
f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
Inverter
Apply to Inverter Chain

In
Out
1
CL
tp = tp1 + tp2 + + tpN
C gin , j 1
t pj ~ Runit Cunit 1
C
gin
,
j
N
N
C gin , j 1
, C gin , N 1 C L
t p t p, j t p0 1
C gin , j
j 1
i 1
Inverter
Optimal Tapering for Given N

Delay equation has N - 1 unknowns, Cgin,2 Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
C gin , j C gin , j 1C gin , j 1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay
Inverter
Optimum Delay and Number of

Stages
When
each stage is sized by f and has same eff. fanout f:
f
F C L / C gin ,1
Effective fanout of each stage:
f NF
Minimum path delay
t p Nt p 0 1 N F /
Inverter
Example
In
C1
Out
1
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
Inverter
Optimum Number of Stages

For a given load, CL and given input capacitance Cin
Find optimal sizing f
ln F
N
C L F Cin f Cin with N
ln f
t p Nt p 0 F
1/ N
/ 1
t p 0 ln F

t p t p 0 ln F ln f 1
ln 2 f
For = 0, f = e, N = lnF
ln f ln f
f
0
f exp1 f
Inverter
Optimum Effective Fanout f

Optimum f for given process defined by
f exp1 f
fopt = 3.6
for =1
Inverter
Impact of Self-Loading on tp
No Self-Loading, =0
With Self-Loading =1
u/ln(u)
60.0
40.0
x=10,000
x=1000
20.0
x=100
x=10
0.0
1.0
3.0
5.0
7.0
Inverter
Normalized delay function of F
t p Nt p 0 1 N F /
Inverter
Buffer Design
1
16
2.8
22.6
tp
64
64
65
64
18
64
15
64
2.8
15.3
Inverter
Power Dissipation
Inverter
Where Does Power Go in CMOS?

Dynamic Power Consumption
Charging and Discharging Capacitors
Short Circuit Currents

Short Circuit Path between Supply Rails during Switching
Leakage
Leaking diodes and transistors
Inverter
Dynamic Power Dissipation

Vdd
Vin
Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.
Inverter
Modification for Circuits with Reduced Swing

Vdd
Vdd
VddVt
CL
E 0 1 = CL Vdd V dd Vt
Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)
Inverter
Adiabatic Charging
2
Inverter
Adiabatic Charging
Inverter
Node Transition Activity and Power

Consider switching a CMOS gate for N clock cycles
E
= C V 2 n N
N
L
dd
EN : the energy consumed for N clock cycles

n(N): the number of 0->1 transition in N clock cycles
EN
2
n N
P avg = lim fclk = lim C Vdd f clk
N N
N N
L
01
n N
lim
N N
P av g = 0 1 C Vdd 2 f clk
L
Inverter
Transistor Sizing for Minimum

Energy
In
Out
Cg1
Goal:
Cext
Minimize Energy of whole circuit
Design parameters: f and VDD

tp tpref of circuit with f=1 and VDD =Vref

f
F

t p t p 0 1 1

f

VDD
t p0
VDD VTE
Inverter
Transistor Sizing (2)
Performance Constraint (=1)
tp
t pref
F
2 f
f VDD Vref VTE
3 F
Vref VDD VTE
t p0
t p 0 ref
F
2 f
f
1
3 F
Energy for single Transition

2
E VDD
C g1 1 1 f F
2
VDD 2 2 f F
E

Eref Vref
4 F
Inverter
Transistor Sizing (3)

VDD=f(f)
E/Eref=f(
f)
1.5
3.5
F=1
normalized energy
2
vdd (V)
2.5
1.5
20
0.5
0
0.5
10
Inverter
Short Circuit Currents

Vdd
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
1.0
2.0
3.0
Vin (V)
4.0
5.0
Inverter
How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,

but cant do this for cascade logic, so ...
Inverter
Minimizing Short-Circuit Power

8
7
6
Vdd =3.3
Pnorm
5
4
Vdd =2.5
3
2
1
0
Vdd =1.5
0
tsin/tsout
Inverter
Leakage
Vdd
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues

Sub-Threshold
in low-energy
circuitCurrent
design!Dominant Factor
Inverter
Reverse-Biased Diode Leakage

GATE
p+
p+
ReverseLeakageCurrent
+
V
dd
IDL=JSA
2
fora1.2mCMOStechnology
JS = 10-100 pA/m2
at 25 deg C for 0.25m CMOS
JS =15pA/m
JS doubles for every 9 deg C!
Jsdoublewithevery9oCincreaseintemperature
Inverter
Subthreshold Leakage Component
Inverter
Static Power Consumption

Vdd
Istat
Vin =5V
Vout
CL
Pstat = P(In=1).Vdd . Istat
Wasted energy
Dominates over dynamic consumption

Should be avoided in almost all cases,
Not a function of switching frequency
but could
help reducing energy in others (e.g. sense amps)
Inverter
Principles for Power Reduction

Prime
choice: Reduce voltage!
Recent years have seen an acceleration in

supply voltage reduction
Design at very low voltages still open question
(0.6 0.9 V by 2010!)
Reduce
switching activity
Reduce physical capacitance
Device Sizing: for F=20
fopt(energy)=3.53, fopt(performance)=4.47
Inverter
Impact of
Technology
Scaling
Inverter
Goals of Technology Scaling

Make
things cheaper:
Want to sell more functions (transistors)

per chip for the same money
Build same products cheaper, sell the
same part for less money
Price of a transistor has to be reduced
But
also want to be faster, smaller,

lower power
Inverter
Technology Scaling
Goals of scaling the dimensions by 30%:

Reduce gate delay by 30% (increase operating
frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
Die size used to increase by 14% per

generation
Technology generation spans 2-3 years
Inverter
Technology Generations
Inverter
Technology Evolution (2000 data)
International Technology Roadmap for Semicondu

Year of
Introduction
1999
Technology node
[nm]
180
Supply [V]
2000
2001
2004
2008
2011
2014
130
90
60
40
30
0.6-0.9
0.5-0.6
0.3-0.6
9-10
10
3.5-2
7.1-2.5
11-3
14.9
-3.6
1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2
Wiring levels
6-7
6-7
Max frequency
[GHz],Local-Global
1.2
Max P power [W]
90
106
130
160
171
177
186
Bat. power [W]
1.4
1.7
2.0
2.4
2.1
2.3
2.5
1.6-1.4 2.1-1.6
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

Inverter
Technology Evolution (1999)
Inverter
ITRS Technology Roadmap

Acceleration Continues
Inverter
Technology Scaling (1)

Minimum Feature Size (micron)
10
10
10
10
-1
-2
10
1960
1970
1980
1990
Year
2000
2010
Minimum Feature Size

Inverter
Number of components per chip

Inverter

tp decreases by 13%/year
50% every 5 years!
Propagation Delay
Inverter

1000
10
1
0.1
0.01
80
MPU
DSP
85
Year
(a) Power dissipation vs. year.
90
95
Power Density (mW/mm 2 )
Power Dissipation (W)
100
100
10
1
1
Scaling Factor
normalized by 4 m design rule
(b) Power density vs. scaling factor.
From Kuroda
Inverter
10
Technology Scaling Models

Full Scaling (Constant Electrical Field)
ideal model dimensions and voltage scale
together by the same factor S
Fixed Voltage Scaling

most common model until recently
only dimensions scale, voltages remain constant
General Scaling
most realistic for todays situation
voltages and dimensions scale with different factors
Inverter
Scaling Relationships for Long Channel Devices
Inverter
Transistor Scaling
(velocity-saturated devices)
Inverter
Processor Scaling
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
Inverter
Processor Power
Inverter
Processor Performance
Inverter
2010 Outlook
Performance 2X/16 months

1 TIP (terra instructions/s)
30 GHz clock
Size
No of transistors: 2 Billion
Die: 40*40 mm
Power
10kW!!
Leakage: 1/3 active Power
Inverter
Some interesting questions

What
will cause this model to break?

When will it break?
Will the model gradually slow down?
Power and power density
Leakage
Process Variation
Inverter

Rabaey Chapter5

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Rabaey Chapter5

Transféré par

Droits d'auteur :

Formats disponibles

Digital Integrated

Digital Integrated Circuits2nd

The CMOS Inverter: A First Glance

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

CMOS Inverter: Transient Response

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

PMOS Load Lines

Digital Integrated Circuits2nd

CMOS Inverter Load Characteristics

Digital Integrated Circuits2nd

CMOS Inverter VTC

Switching Threshold as a function

Digital Integrated Circuits

Determining VIH and VIL

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Gain as a function of VDD

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Impact of Process Variations

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

CMOS Inverter Propagation Delay

CMOS Inverter Propagation Delay

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Design for Performance

Digital Integrated Circuits2nd

Delay as a function of VDD

Digital Integrated Circuits2nd

(for fixed load)

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Impact of Rise Time on Delay

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

tpLH = (ln 2) RPCL

Inverter with Load

Inverter with Load

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

Apply to Inverter Chain

tp = tp1 + tp2 + + tpN

Optimal Tapering for Given N

Optimum Delay and Number of

Effective fanout of each stage:

CL/C1 has to be evenly distributed across N = 3 stages:

Digital Integrated Circuits2nd

Optimum Number of Stages

Optimum Effective Fanout f

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Normalized delay function of F

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Digital Integrated Circuits2nd

Where Does Power Go in CMOS?

Short Circuit Currents

Digital Integrated Circuits2nd

Dynamic Power Dissipation