FETs 1

Lecture 2
10/10/2004

Course Content
Op-amps
FETs
Oscillators
A/D

& D/A converters

Lecture Content
Revision

of p-n junction diodes

The FET family
The JFET (n-channel)
JFET Models and Biasing
The IGFET (n-channel)
MOSFETs
Sample & Hold Circuit

Revision of p-n junction diode

Diagrams from "Electronic Principles", EPT Educational Software, available in D411/D421

Revision of p-n junction diode

No

bias: Hole-electron re-combination at the

junction forms a depletion layer
Forward bias: p-type (anode) positive w.r.t. ntype (kathode) decreases the depletion layer
and forward current will eventually flow when
the bias exceeds about 0.6 - 0.7 V.
Reverse bias. p-type (anode) negative w.r.t.
n-type (kathode) widens the depletion layer
and only re-combination and thermal currents
flow. A very small reverse current will flow.

Lecture Content
Revision

of p-n junction diodes

The FET family
The JFET (n-channel)
JFET Models and Biasing
The IGFET (n-channel)
MOSFETs
Sample & Hold Circuit

FET Family
Junction Gate (JFET or JUGFET)

Insulated Gate (IGFET)

MOSFET

n-channel & p-channel

Depletion

n-channel & p-channel

Enhancement
n-channel & p-channel

Characteristic of JFET
(n-channel)
Drain (D)
D
G
Gate (G)
p

Ohmic
contacts

Depletion
region

Source (S)

Gate Voltage (VGS ) at ground

VDS > 0

Gate voltage (VGS = 0) (contd)

D

ID
IDSS

Saturation level (VGS = 0V)

n-channel resistance (rDS)

S
0

VP

VDS

Gate voltage (VGS = 0) (contd)

In the ohmic region, drain current (ID) increases in

proportion to VDS

Eventually the depletion layer will pinch-off the

channel towards the drain end.
However, any further increases in VDS also increase
the depletion layer, restricting increases in ID, which
will level off at the saturation current IDSS

IDSS:

maximum drain current defined when VGS = 0

and VDS > |VP|

Gate voltage (VGS<0)

ID

Ohmic
Region

IDSS

I D
gm
VGS

VGS = 0V
VGS = -1V

VGS

I D
VGS

-4

VGSoff
VP

-3

Saturation region

VGS = -2V
VGS = -3V
-2

-1

VGS = -4V
|VP|

VDS

Gate voltage (VGS<0) (Contd)

Increasing

VGS negatively for a given VDS

widens the depletion layer, reducing current
flow (ID)

The

depletion layer will extend right across the

channel, and current flow will cease at the
threshold voltage (VTH)

The

slope of the ID vs VGS characteristic at a

value of VGS determines the
transconductance of the device (gm)

Characteristics

Transfer Characteristic (Shockleys equation)

Plot of output current (ID) vs input voltage (VGS)

VGS
I D I DSS 1
VP

Drain Characteristic

Plot of the joining points where pinch-off occurs

VDS ( SAT )
I D I DSS
V

Gate voltage (VGS>0)

Reduces

the depletion layer

So the current (ID) increases
When

the p-n junction starts to become

forward biased, the gate current flows into the
gate
Electrons are withdrawn from the channel
Then ID falls

JFET vs BJT
Advantages

of FETs over BJTs:

JFETs are usually operated at negative VGS when

gate current is negligible i.e. a very high input
resistance
Only one major charge carrier (2 in BJTs) reduces
shot noise
They switch faster when used as switches
They can operate from much higher logic levels
increasing their noise immunity.

Example of n-channel JFET

n-channel JFET (or JUGFET)
Type 2N3369. Vth = -2.07 V
Drain

Id
Vds

Gate
Vgs

Source

Example (Contd)
ID vs VDS
2.00m

VGS = 0V

Id [A]

1.50m

1.00m

VGS = -1V

500.00u

0.00
0.00

1.00

2.00
Vds [V]

3.00

4.00

Example (Contd)
ID vs VGS
3.00m

VDS = 2V
Id [A]

2.00m

1.00m

0.00
-3.00

-2.00

-1.00
Vgs [V]

0.00

1.00

JFET (p-channel)
Drain (D)

D
G
Gate (G)
p

p
S

Ohmic
contacts

Depletion
region

Source (S)

JFET (p-channel) (contd)

All

voltage polarities are reversed, with the

arrow in the symbol also reversed.

 Revision

of p-n junction diode

The FET family
The JFET (n-channel)
JFET Models and Biasing
The IGFET (n-channel)
MOSFETs
Sample & Hold Circuit

JFET Models and Biasing

Input
iD

= gm.vgs

Drain

gate
vgs

signal vgs produces a drain current iD

source resistance rDS
drain

gm.vgs

source

rds

AV

v ds

g m .rds
v gs

JFET Models
This

model is quite satisfactory for low

frequency (audio) applications.

At

higher frequencies (RF) any gate

capacitance becomes significant (see later
with MOSFETs).

Small-Signal JFET Amplifier

Rd = 11k
R2 = 730k

C2

Vdd = 12V

Vout

C1

Vin

2N3369

R1 = 20k
Rs = 1k

Cs

Rl = 10k

Small-Signal JFET Amplifier

(contd)
Most

common bias circuit

Gate current = 0 (unlike base current)
VGS < 0 for n-channel JFET
VG

>0

Small-Signal JFET Amplifier:

DC Analysis
Taking

the bias operating point as:

VGS = 0.5V

VDS = 2V

then ID 820A taken from the FET

3.00m
characteristics
Id [A]

2.00m

1.00m

0.00
-3.00

-2.00

-1.00
Vgs [V]

0.00

1.00

Small-Signal JFET Amplifier

DC Analysis (contd)

DC Analysis

R2

Rd

Vdd = 12V
2N3369

R1

Rs

Small-Signal JFET Amplifier

DC Analysis (contd)
VDD I D Rd Rs VDS
VGS VG I D Rs
Design

bit

Rd needs to be large for the gain

Rs is made not too small

Vs = Id x Rs could be below 0.5V so that Vg would

need to be negative

Small-Signal JFET Amplifier

DC Analysis (contd)
Let's

try Vs = 0.82V so that Vg needs to be

0.32V.
Therefore Rs = 1k, Rd = 11k.

R1
VG
.VDD
R1 R2
R2

= 36.5 R1 then R1 = 20k & R2 = 730k

Small-Signal JFET Amplifier

DC Analysis (contd)
Some of the resistor values are not preferred
Therefore a re-iteration of the calculations is
required when preferred values are selected
Using simulator, the design process of
design, simulate, re-iterate and test is
achieved
Using TINA, the following results are obtained:

Vg = 0.32V; Vs = 0.83V; Vgs = -0.51V;

Vds = 2V; Vd = 2.83V; Id = 0.83mA

Small-Signal JFET Amplifier:

AC Analysis
AC

Analysis
g

d
g .v
m gs

Vin

R1 = 20k

R2 = 730k

Rds= 110k

Rd = 11k
Rl = 10k

Small-Signal JFET Amplifier:

AC Analysis (contd)
The

values of rDS and gm are obviously

required:

Datasheet
Output characteristic and transfer characteristic
using TINA or datasheet

For

this JFET, rDS = 110k and gm = 1.1mS

Small-Signal JFET Amplifier:

AC Analysis (contd)
Thus

the voltage gain is

vout
Av
g m .Rx
vin
where Rx = Rds//Rd//R1 = 5k

Hence

Av = 5.5 = 14.8dB

Small-Signal JFET Amplifier:

AC Analysis (contd)
Remember

that these are small signal

devices
A sensible maximum input swing is 50mV
Otherwise, distortion will set in until
eventually the output voltage totally "bottoms"
at -1V and "clips" at +4.4V

Q & A?