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DIGITAL LOGIC DESIGN

(DLD)

Lecture # 11

Sequential Circuits

University of Management & Technology

LATCHES

latch is a temporary storage device that has

two stable states (bistable). It is a basic form of


memory.
Latch

is similar to Flip-flop.

Difference

between

latch

and

method of changing their state.

flip-flop

is

S-R (SET-RESET) LATCH

The S-R (Set-Reset) latch is the most basic type. It can


be constructed from NOR gates or NAND gates. With
NOR gates, the latch responds to active-HIGH inputs;
with NAND gates, it responds to active-LOW inputs.

Q
S

NOR Active-HIGH Latch

Q
S

NAND Active-LOW Latch

S-R (SET-RESET) LATCH

The active-HIGH S-R latch is in a stable


(latched) condition when both inputs are LOW.

Assume the latch is initially


RESET (Q = 0) and the inputs are
at their inactive level (0). To SET
the latch (Q = 1), a momentary
HIGH signal is applied to the S
input while the R remains LOW.
To RESET the latch (Q = 0), a
momentary HIGH signal is
applied to the R input while the
S remains LOW.

S-R (SET-RESET) LATCH

The active-LOW S-R latch is in a stable (latched)


condition when both inputs are HIGH.
Assume the latch is initially
RESET (Q = 0) and the inputs
are at their inactive level (1).
To SET the latch (Q = 1), a
momentary LOW signal is
applied to the S input while
the R remains HIGH.
To RESET the latch a
momentary LOW is applied
to the R input while S is
HIGH.

S-R (SET-RESET) LATCH

Never apply an active set and reset at the same


time (invalid).

Feedback is the characteristic of flipflops.

A latch can reside in either set or reset states.

THE GATED S-R LATCH

A gated latch is a variation on the basic latch.

The gated latch has an additional input, called


enable (EN) that must be HIGH in order for the
latch to respond to the S and R inputs.

THE GATED S-R LATCH

LOGIC SYMBOL OF THE GATED S-R LATCH

THE D LATCH

The D latch is an variation of the S-R latch but


combines the S and R inputs into a single D
input as shown:

A simple rule for the D latch is:


Q follows D when the Enable is active

THE GATED D LATCH

The truth table for the D latch summarizes its


operation. If EN is LOW, then there is no change
in the output and it is latched.

Inputs

Outputs

EN

Comments

0
1
X

1
1
0

0
1
Q0

1
0
Q0

RESET
SET
No change

FLIP-FLOPS

Flipflops are bistable devices also known as


bistable multivibrators.

A flip-flop differs from a latch in the manner it


changes states. A flip-flop is a clocked device, in
which only the clock edge determines when a new
bit is entered.

Edge triggering changes state at either positive


edge or negative edge of the clock pulse.

THE EDGE TRIGGERED FLIP-FLOPS

EDGED-TRIGGERED S-R FF

EDGED-TRIGGERED S-R FF

EDGED-TRIGGERED S-R FF

EDGE-TRIGGERED D FF
The

truth table for a positive-edge triggered

D flip-flop shows an up arrow to remind you


that it is sensitive to its D input only on the
rising edge of the clock; otherwise it is
latched. The truth table for a negative-edge
triggered D flip-flop is identical except for
the direction of the arrow.

EDGE-TRIGGERED D FF

EDGE-TRIGGERED D FF

EDGE-TRIGGERED JK-FF
JK-FF

is versatile and is a widely used

type of flip-flop.
The

functioning of the JK-FF is identical

to that of the SR-FF in the SET, RESET,


and NC.
The

difference is that the JK-FF has

NO invalid state as does the SR-FF.

EDGE-TRIGGERED JK-FF
The

J-K flip-flop is more versatile than the

D flip flop. In addition to the clock input, it


has two inputs, labeled J and K. When
both J and K = 1, the output changes
states (toggles) on the active clock edge (in
this case, the rising edge).

EDGE-TRIGGERED JK-FF

EDGE-TRIGGERED JK-FF

FLIP-FLOP CHARACTERISTICS
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of
the clock to the 50% level of the output transition

FLIP-FLOP CHARACTERISTICS

SEQUENTIAL CIRCUITS
Sequential circuits has an extra dimension time.
Combinational circuit output depends only on the present inputs
Sequential circuit output depends on the history of past inputs
as well

More powerful than combinational circuit, able to model


situations that cannot be modeled by combinational circuits

Building blocks of synchronous sequential logic circuits: gates


and flip-flops.

Flip-flops make up the memory M while the gates form one or


more combinational subcircuits C1, C2, , Cq.

25

SEQUENTIAL CIRCUIT ANALYSIS


Given a sequential circuit diagram, analyze its behaviour
by deriving its state table and hence its state diagram.

Requires state equations to be derived for the inputs, as


well as output functions for the circuit outputs.

We use A(t) and A(t+1) to represent the present state and


next state, respectively, of a flip-flop represented by A.

Alternatively, we could simply use A and A+ for the present


state and next state respectively.
26

SEQUENTIAL CIRCUIT ANALYSIS


From the state equations and output function, we
derive the state table, consisting of all possible
binary combinations of present states and inputs.

State table
Similar to truth table.
Inputs and present state on the left side.
Outputs and next state on the right side.

m flip-flops and n inputs 2m+n rows.

27

SEQUENTIAL CIRCUIT ANALYSIS


Example:
State equations:
A+ = A.x + B.x
B+ = A'.x

Output function:
y = (A + B).x'
D

CP

Q'

A'

Q'

B'
y

Figure 1.

28

SEQUENTIAL CIRCUIT ANALYSIS


State table for the circuit of Figure 1:
State equations:
A+ = A.x + B.x
B+ = A'.x
Present
State
A B
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

Output function:
y = (A + B).x'

Input
x
0
1
0
1
0
1
0
1

Next
State
A+ B+
0
0
0
1
0
1
0
1

0
1
0
1
0
0
0
0

Output
y
0
0
1
0
1
0
1
0
29

SEQUENTIAL CIRCUIT ANALYSIS


From the state table, we can draw the state diagram.
State diagram

Each state is denoted by a circle.


Each arrow (between two circles) denotes a transition of

the sequential circuit (a row in state table).


A label of the form a/b is attached to each arrow where a
denotes the inputs while b denotes the outputs of the
circuit in that transition.

Each combination of the values represents a state.


Hence, m up to 2m states.

30

SEQUENTIAL CIRCUIT ANALYSIS


State diagram of the circuit of Figure 1:
Present
State
AB
00
01
10
11

Next State
x=0
x=1
+ +
A B A +B +
00
00
00
00

01
11
10
10

Output
x=0 x=1
y
y
0
1
1
1

0
0
0
0

0/0

0/1

00
1/0

0/1
01

0/1
1/0

1/0
10
1/0
11
31

INPUT FUNCTIONS
The outputs of a sequential circuit are functions of the present
states of the flip-flops and the inputs. These are described
algebraically by the circuit output functions.
In Figure 1: y = (A + B).x'

The part of the circuit that generates inputs to the flip-flops


are described algebraically by the flip-flop input functions (or
flip-flop input equations).

The input functions determine the next state generation.


From the flip-flop input functions and the characteristic tables
of the flip-flops, we obtain the next states of the flip-flops.

32

FLIP-FLOP INPUT FUNCTIONS


Example: circuit with a JK flip-flop.
We use 2 letters to denote each flip-flop input: the first
letter denotes the input of the flip-flop (J or K for JK
flip-flop, S or R for SR flip-flop, D for D flip-flop, T for T
flip-flop) and the second letter denotes the name of the
flip-flop.
JA = B.C'.x + B'.C.x
KA = B + y

B
C'
x
B'
C
x'

J
B
y

K Q'
CP

33

FLIP-FLOP INPUT FUNCTIONS


In Figure 1, we obtain the following state equations
by observing that Q+ = DQ for a D flip-flop:
A+ = A.x + B.x
(since DA = A.x + B.x)
B+ = A'.x (since DB = A'.x)
x

D
CP

Figure 1.

Q'

A'

Q'

B'
y
34

ANALYSIS: EXAMPLE
Given Figure 2, a sequential circuit with two JK flipflops A and B, and one input x.

J
x

K Q'

K Q'

Figure 2.
Obtain the
flip-flop input functions from the circuit:
CP

JA = B
JB = x'
KA = B.x'
KB = A'.x + A.x' = A x

35

SEQUENTIAL CIRCUIT DESIGN


Design procedure:
Start with circuit specifications description of circuit

behaviour.
Derive the state table.
Perform state reduction if necessary.
Perform state assignment.
Determine number of flip-flops and label them.
Choose the type of flip-flop to be used.
Derive circuit excitation and output tables from the state
table.
Derive circuit output functions and flip-flop input functions.
Draw the logic diagram.
36

SUMMARY
Sequential

circuits have memory and they are more


powerful than combinational circuits.
Analyzing sequential circuits
Flip-flop characteristic table
State Table
State diagram

Designing sequential circuits


State assignment
Circuit output function
Flip-flop input function

37

FULL EXAMPLE 1

Analyze this circuit?


Is this a sequential
circuit? Why?
How many inputs?
How many outputs?
How many states?
What type of
memory?

EXAMPLE 1 (CONT.)
D Flip Flop (review)

Characteristic Tables and Equations

Q(t)

Q(t+1)

Q(t+1)

Q(t+1) = D

EXAMPLE 1 (CONT.)

EXAMPLE 1 (CONT.)

State equations:

DA = AX + BX

DB = A X

Y = (A + B) X

EXAMPLE 1 (CONT.)

State equations:

DA = AX + BX

DB = A X

Y = (A + B) X

State table:

EXAMPLE 1 (CONT.)

State equations:

DA = AX + BX

DB = A X

Y = (A + B) X

State table (2D):

EXAMPLE 1 (CONT.)

State equations:

DA = AX + BX

DB = A X

Y = (A + B) X

State table:

State diagram: