Phase Lock Loop

OBJECTIVES
Introduction to Phaselocked loop (PLL)
Historical Background
Basic PLL System
Phase Detector (PD)
Voltage Controlled
Oscillator (VCO)
Loop Filter (LF)
PLL Applications

Introduction to Phaselocked Loop (PLL)

PLL is also referred as frequency synthesizer.
PLL is a circuit that locks the phase of the output to the input.
PLL is a negative feedback control system where fout tracks fin
and rising edges of input clock align to rising edges of output
clock
PLL is a circuit synchronizing an output signal with a
reference or input signal in frequency as well as in phase.
In the synchronized or locked state, the phase error
between the oscillators output signal and the reference
signal is zero, or it remains constant.
If a phase error builds up, a control mechanism acts on the
oscillator to reduce the phase error to a minimum so that
the phase of the output signal is actually locked to the
phase of the reference signal. This is why it is called a
phase-locked loop.

How Are PLLs

Used?

Brief Phase-Locked Loop (PLL) His

1932: Invention of coherent communication
using vacuum tube, (deBellescize)
1943:
Horizontal
and
vertical
sweep
synchronization in television (Wendt and Faraday)
1954: Color television (Richman)
1965: PLL on integrated circuit
1970: Classical digital PLL
1972: All-digital PLL
PLLs today: in every cell phone, TV, radio, pager,
computer,

Clock and Data Recovery

Frequency Synthesis
Clock Generation
Clock-skew minimization
1.people.ee.duke.edu/~mbrooke/defense/Borte.ppt
Duty-cycle enhancement

Basic PLL System

The basic PLL block diagram consists of three components
connected in a feedback loop :
A phase detector (PD) or phase frequency detector (PFD)
The phase detector
A voltage-controlled oscillator (VCO)
produces a signal V
A loop filter (LF)
proportional to the phase
difference between the
incoming signal and the VCO
output signal.
The output of the phase
detector is filtered by a lowpass loop filter. The filter
output voltage Vo controls the
frequency of the VCO.
A basic property of the PLL is that it attempts
to maintain
the
The
voltage at
the input of
frequency lock fosc= fi between Vosc and Vithe
even
if the
frequency
fi of
VCO
determines
the
the incoming signal varies in time.
frequency fosc of the periodic
Suppose that the PLL is in the locked condition,
theoutput of the
signaland
Voscthat
at the
frequency fi of the incoming signal increases slightly. The phase
VCO.
difference between the VCO signal and the incoming signal will begin
to increase in time.

Locked Range and Capture Range

of the PLL

Locked condition: fosc = fi

Unlocked condition: fosc = fo = co
Lock Range of the PLL: The range of frequencies from fi = fmin to fi =
fmax where the locked PLL remains in the locked condition. The lock range
is wider than the capture range.
If the PLL is initially locked, and if fi < fmin, or fi > fmax the PLL
becomes unlocked fi fosc. When the PLL is unlocked, the VCO
oscillates at the frequency fo called the center frequency, or the freerunning frequency of the VCO.

Locked Range and Capture Range

PLL
Onceof
thethe
PLL is
in the locked condition, it remains locked as long
as the VCO output frequency fosc can be adjusted to match the
incoming signal frequency fi fmin fi fmax.
When the lock is lost, the VCO operates at the free-running
frequency fo, fmin fo fmax.
To establish the lock again, i.e. to capture the incoming signal
again, the incoming signal frequency fi must be close enough to fo
fo fc fi fo+ fc . The 2fc is called the capture range.
The capture range 2fc is an important PLL parameter because it
determines whether the locked condition can be established or
not. Note that the capture range 2fc < the lock range fmax fmin.
The capture range 2fc depends on the characteristics of the loop
filter. For the simple RC filter, a very crude, approximate implicit
expression for the capture range can be found as:

where fp is the cut-off frequency of the filter, VDD is the supply

voltage, and Ko is the VCO gain.

Phase Detector
A simple phase detector
is an XOR
(PD)
gate with logic low output (V = 0V)

and the logic high output (V = VDD).

An example below shows the PLL is in
the locked condition where Vi and Vosc
are two phase-shifted periodic squarewave signals at the same frequency
fosc = fi = , and with 50% duty ratios.
The output of the phase detector is a
periodic square-wave signal V(t) at
the frequency 2fi , and with the duty
ratio D that depends on the phase
difference (t) = [osc(t) - i(t)] between
Vi and Vosc D =
(for XOR)
The output of the XOR phase detector
can be written as the Fourier series:

The dc component Vo of the phase

The
average output rise to Vout = when goes from
For > , the average output begins to drop.

Loop Filter
The
output V(t) of the phase detector is filtered by the low-pass loop
filter. The purpose of the low-pass filter is to pass the dc and lowfrequency portions of V(t) and to attenuate high-frequency ac
components at frequencies 2kfi . The simple RC filter has the transfer
function:
F(s) = =
where p = and fp = is the cut-off frequency of the filter.
If fp << 2fi the output of the filter Vo is approximately equal to the
dc component V of the phase detector output.
In practice, the high-frequency components are not completely
eliminated
In general, the filter output Vo as a
and can be observed as high-frequency ac ripple around the dc or
function
of the V
phase
difference. Note
slowly-varying
o.
that Vo = 0 if Vi and Vosc are in phase
( = 0), and that it reaches the
maximum value Vo = VDD when the
two signals are exactly out of phase
(( = ).
For 0 , Vo increases, and for >

Voltage Controlled
In
PLL applications, Oscillator
the VCO is treated as
a linear, time-invariant system.
(VCO)

To obtain an arbitrary output frequency (within the VCO tuning range), a

finite Vo is required. Lets define osc i = .
The XOR function produces an output pulse whenever there is a phase
misalignment. Suppose that an output frequency 1 is needed. From the
upper right figure, we see that a control voltage V1 will be necessary to
produce this output frequency. The phase detector can produce this V 1
only by maintaining a phase offset at its input. In order to minimize the
required phase offset or error, the PLL loop gain, KD KO, should be
maximized, since =
The VCO gain is
defined as:
Ko =

VCO Example
The filter output Vo controls the VCO, i.e., determines the frequency fosc
of the VCO output Vosc . From PLL 4046 circuit below, the voltage Vo
controls the charging and discharging currents through capacitor C1. As
a result the frequency fosc of the VCO is determined by the Vo. The VCO
The
VCO
characteristics

arefosc.
output Vosc is a square wave with 50%
duty
ratio
and
frequency
adjustable by three components:
R1, R2 and C1.
When Vo = 0, the VCO operates at
the minimum frequency fmin given
approximately by:

fmin =
When Vo = VDD, the VCO operates at
the minimum frequency fmax given
approximately by:
fmax = fmin+
For fmin fosc fmax, the VCO output
frequency fosc is ideally a linear
function of the control voltage Vo.

Examples
Problem 1.
Determine the change in frequency for a voltage controlled oscillator
(VCO) with a transfer function of KO = 2.5KHz/V and a DC input voltage
change of VO = 0.8V.
Solution:
f = VO KO f = (0.8 V)(2.5 kHz/V) = 2 kHz
Problem 2.
Calculate the voltage at the output of a phase comparator with a
transfer function of KD = 0.5V/rad and a phase error of V = 0.75 rads.
Solution:
VD = KD V = (0.5 V/rad)(0.75 rad) = 0.375 V
Problem 3.
Determine the hold in range, (i.e. the maximum change in frequency)
for a phase lock loop with an open loop gain of KV = 20kHz/rad.
Solution:
fmax = KV /2 = (20 krad) /2 rad = 31.4 kHz
Problem 4.
Find the phase error necessary to produce a VCO frequency shift of f
= 10KHz for an open loop gain of
KV = 40KHz/rad.
Solution:
V = f / KV = 10 kHz / 40 kHz/rad) = 0.25 rad
Problem 5:
Given fosc = 1.2 MHz at VCOin = 4.5 V and fosc = 380 kHz at VCOin = 1.6

Overall PLL system

First we will consider the PLL with feedback = 1;
therefore, input and output frequencies are
identical. The input and output phase should
track one another, but there may be a fixed
offset depending on the phase detector
implementation.
Vi

V
os
c

Frequency and phase tracking loop

We will start from the open loop gain, T(s).
T(s) = KDF(s)KO/s
F(s) is a simple LPF with a cutoff (3 dB) frequency 1
= 1/RC.

Then, T(s) becomes second order, Type 1:

Frequency and phase tracking loop

It is sometimes useful to define a natural frequency, n, and a
damping factor, . This is standard control system
terminology for a second order system. The key is to put the
denominator of the closed loop transfer function, 1 + T(s),
into a standard form:
either

s 2 + 2 n s + n 2

or + 1

Taking the first formula, 1 + T(s) can be written as:

so, we can associate n and with:

Example
A phase-locked loop has a center frequency of 0 = 105 rads, KO =
103 rad/s per V, and KD = 1 V/rad. There is no other gain in the loop.
Determine the overall transfer function H(s) for:
a) The loop filter is F(s) = 1.
b) The loop filter F(s) is shown below.

1 = 1/RC
= 1/(120k
x3.3nF) = 2525

Example
Consider a PLL with KO = 250 krad s per V and that
uses a Type I (XOR) phase detector KD = Vcc / . The
supply voltage is 5 V, and a simple RC filter (see
below) is used. For the filter R = 120 k and C = 3.3
nF. There is no other gain in the loop.
a) Determine the transfer function H(s) = o(s)
i(s) of the loop.

b) Calculate natural frequency n and damping ratio

.

Synthesizer PLL
We will now add the divider 1/N to the
feedback path. This architecture is called
an integer-N synthesizer.

We can calculate the loop gain, T(s):

Loop gain is reduced by a factor of N.

In most applications, N is not constant, so KV = KDKO is not a
constant varies with frequency according to the choice of N

Synthesize PLL