Académique Documents
Professionnel Documents
Culture Documents
Charlton S. Inao
Professor Mechatronics
Defence University
Coolege of Engineering
Bishoftu, Ethiopia
General Objectives
To explain and understand the
following concept:
1. System
2. Architecture
3. Instructions
4. Communication Interface
5. Microcontrollers
6. Memory, Input Output
7. Programming Applications
Microprocessor
The central processing unit (CPU) is the "brain"
of a computer.It is the part of thecomputer
which interprets and carries out instructions
from the computer programs.
Modern
desktop
computers
use
microprocessors: complex integrated circuits
containing millions of transistors and other
electronic components. The microprocessor is
mounted in a socket or slot on the mainboard
(motherboard) so that it can be connected to
other components.
Parallel Interface
Microprocessor Organization
Microprocessor Organization
ALU
The actual work of the microprocessor is
carried out in the Arithmetic Logic Unit. Most of
these operations are in fact performed by
addition. To perform subtraction, the CPU first
finds the complement of the number to be
subtracted and then adds the two numbers.
Multiplication and division can be performed
by carrying out multiple addition or subtraction
operations. To compare two numbers, the CPU
will subtract them and then check to see if
there is a remainder, and so on.
REGISTERS
In order to carry out its operations, the processor
has storage locations, called registers, for the
numbers and instructions it is operating on.
For example, to add two numbers, the first number
mign be loaded into Register A, the second into
Register B and the result stored in Register C.
To speed up the operations of the processor, the
Prefetch unit looks ahead in the program to find the
next instructions and preloads them into registers,
to cut down on time wasted waiting for the next
instruction.
Registers
Most of the registers contain
data/instruction offsets within 64 KB
memory segment. There are four
different 64 KB segments for
instructions, stack, data and extra
data. To specify where in 1 MB of
processor memory these 4 segments
are located the processor uses four
segment registers:
Accumulatorregister consists of 2
8-bit registers AL and AH, which can
be combined together and used as a
16-bit register AX. AL in this case
contains the low-order byte of the
word, and AH contains the high-order
byte. Accumulator can be used for
I/O
operations
and
string
Buses
The microprocessor connects to the external
components of the computer via "buses": sets of
parallel conductors used to move data in the form
of electrical pulses.
There are three types of buses: thedata
buscarries the binary-coded information and
instructions;
theaddress buscarries binary-coded numbers
which identify storage locations in main memory,
much like the postal code on a letter;
thecontrol buscarries timing signals, read-write
signals, interrupt requests and similar signals
between the microprocessor and external devices
To manage the flow of data into and out of the CPU, two other
units are required: the Memory Management Unit, and the Bus
Management Unit. To summarize, the essential sections of a
microprocessor are:
Arithmetic Logic Unit:executes all logic and arithmetic
operations as specified by the instruction set
Control Unit:contains the microcode that tells the ALU how to
function.
Decode Unit:translates instruction into control signals and
microcode directions then queues them until requested by the
Control Unit.
Prefetch Unit:queues instruction to assure that the
microprocessor is in continuous operation.
Memory Management Unit: converts internal logic
addresses into external memory addresses.
Bus Management Unit:manages the flow of information
between the microprocessor and data storage locations (main
disk, CD-ROM, etc.) and peripherals ( printer, monitor, etc.)
Many
of
the
refinements
in
modern
microprocessors are designed to improve
processor utilization and eliminate wasted clock
cycles. The addition of cache memoryhighspeed memory used for temporary storage of
instructions and data; multiple "pipelines" so that
more than one sequence of instructions can be
performed at one time; Branch-prediction units
which attempt to predict which branch of a
program will be executed next so that the cache
memory and extra piplines can be used efficiently.
Microprocessor Specifications
As processor speeds increased, the speed of main memory (RAM) could not keep up.
To minimize size and cost, RAM memory uses Dynamic RAM (DRAM). Static RAM
(SRAM) is much faster, but also more expensive, so it is used in small quantities as a
temporary storage location for data on the microprocessor or closely connected to it.
This high-speed memory is known as cache memory. It is operated by a cache
controller which attempts to identify which data or instructions will be needed next
and load them into the cache so that the processor will not have to stand idle while
waiting for data to be retrieved from RAM.
Today's microprocessors have cache memory in two levels, referred to as Level 1
(L1)and Level 2 (L2). The L2 cache was originally mounted on separate chips outside
the CPU, and operated at a lower speed than the processor, but improvements in
manufacturing technology have permitted the L2 cache to be moved onto the
processor chip where it operates at the same speed as the processor. In processors
like the Pentium III, an additional external bus operating at processor speed connects
the L2 cache; this is known as the backside bus in contrast to the frontside bus
Clock
Clock Speed
An oscillator mounted on the motherboard generates a series of
electrical pulses which the computer uses to synchronize the
operations of its many components. Each complete change in
the signal, from positive to negative and back again is known as
a cycle, and the number of cycles per second, or frequency, is
measured in Hertz.
1 000 Hz = 1 kilohertz = 1KHz
1 000 000 Hz = 1 Megahertz = 1 MHz
1 000 000 000 Hz = 1 Gigahertz = 1 GHz.
The speed of the processor is often a multiple of the external bus
speed: for example a 500 MHz chip installed on a 100MHz
mainboard will operate at 5x the bus speed.
Clock
The clock signals in microprocessor system
are timing waveforms that are used to
synchronize the systems operation. Some
microprocessors have an internal oscillator
to generate a clock signal. These
microprocessors require only external,
passive
timing
components.
Other
microprocessors do not have an internal
oscillator , and require more complicated
external circuitry to generate the clock
waveforms.
MIPS
The clock speed does not relate directly to the speed at which the CPU
processes instructions. Early microprocessors required as many as 10 clock
cycles to complete a single instruction. Modern microprocessors with what
is called 'superscalar" architecture have dual or multiple 'pipelines' so that
more than one instruction can be executed at once. Therefore, a more
accurate measure of processor speed is MIPS (Millions of Instructions per
Second), although the number of actual instructions processed rarely
reaches the theoretical maximum.
Power consumption
Core I7 by Intel
Intel is soon going to be bringing the fastest mobile processors, it's first of the Core-i7
for notebooks. There are three processors in this list and all three
Intel Core I7
Instruction/Microprocessor Machine
Language(8080/8085)
APPLICATION PROGRAMS
OUT
output
INT 3
CALL
JMP
JNZ
RET
END
DEC
End of Program
Decrease/decrement
INC
Increase/increment
ROR
Rotate Right
ROL
Rotate LEFT
LEA
TAB
Table/tabulation
CMP
Compare
CS
Code Segment
DB
Define Byte
DW
Define Word
CODE SEGMENT
Code segment(CS) is a 16-bit
register containing address of 64 KB
segment with processor instructions.
The processor uses CS segment for
all
accesses
to
instructions
referenced by instruction pointer (IP)
register.
CS register cannot be changed
directly.
The
CS
register
is
automatically updated during far
Example no . 1
All LEDs turned ON
1
2
3
4
F=15
(HEXADECIMAL)
Example No . 2
All lights ON and OFF with delay in between
1
ORG 100 H
2
3
4
6
7
8
9
OUT 53H, AL
JMP TOP
10
11
12
13
14
15
16
JNZ L1
RET
END
Example No . 3
4 right most LEDs ON, then 4 leftmost LEDs ON,
alternatively
Example No. 3
8
DLY: MOV BL, a delay 0AH (approximately 10 seconds) is to be moved in
accumulator BL
9 0Ah
L1: MOV CX, , loop1, Accumulator C (16 bit), complete logic 1 of 16 bit for
decrement timing
10 FFFF H
looping L2
11 L2: LOOP L2
decrement Accumulator B, low part (BL)
12 DEC BL
Jump no Zero, jump to L1 ( CX=FFFF) if not
zero..FFFF,FFFE,FFFD,FFFC,FFFB,FFFA0000
13 JNZ L1
RETURN
14 RET
1
ORG 100 H
TOP: MOV
Al, Fh
OUT 53h, Al
CALL DLY
MOV AL, ,
Fh
ROTATE LEFT(ROL)
ORG 100 H
origin a t 100 H, kit start assigned address
: MOV Al, 1 move data 0F in Accumulator A,low. To the right most
h
LED going to left most LED
TOP: OUT
put the contents accumulator to RAM kit address 53H,
53h, Al
in the label TOP
CALL DLY
calling a subroutine program for delay (DLY)
Rotate left(ROL),,in the incremental step of 1(sequence
ROL Al, 1
of 1 step increment interval towards the left)
putting the output of accumulator which is ALL
OUT 53H, AL OFF(logic 0), to to address 53H
JMP TOP
jump to label:TOP
INT 3
interrupt or stop the program
END
END/Terminate /Stop program
a delay counter starting value of FFFFh (complete or
DLY: MOV
longest 16 bit of logic 1)
CX, 0FFFFh
is to be moved in accumulator CX(16 bit)
L1: LOOP L1
RET
RETURN to the Start
END
end of program
LEFT
ROTATE RIGHT(ROR)
ORG 100 H
: MOV Al,
80h
TOP: OUT
53h, Al
CALL DLY
1
2
3
4
5
6
7
8
8
1
0
0
0
0
0
0
0
4
0
1
0
0
0
0
0
0
2
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
8
0
0
0
0
1
0
0
0
4
0
0
0
0
0
1
0
0
2
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
8
4
2
1
0
0
0
0
0
0
0
0
8
4
2
1
Programming a
Stepper Motor
Using 8086
Microprocessor
Programming a
Stepper Motor 90,
180, 360 degrees
Using 8086
Microprocessor
Lamp
Color
ORG 100 H
TOP: MOV AL,14 H
Green, Red
yellow
green/ Red
Yellow
OUT 53 ,AL
CALL DLY 2
MOV AL, 36H
OUT 53H,AL
CALL DLY 1
MOV AL,41 H
OUT 53H,AL
Red, Green
Red
Yellow
CALL DLY 2
MOV AL,63H
Annotation
DEC BL
Decrement Accumulator B l
JNZ
Jump No Zero
RET
Return
END
DLY1:MOV BL,OAH
L3:MOV CX,OFFFFH
L4: LOOP L4
DEC BL
Jump No Zero
JNZ L3
Jump if No Zero
RET
Return
END
bit assignment
Course Outline
Microprocessor Based Products
Programming Applications
New Developments
Microcontrollers VS
microprocessor
Embedded microprocessor
products
Criteria for microprocessor
selection
Microprocessor
Based Products
Toys/game console
Playstation/Xbox/Nintendos
Wii
Calculator
Traffic Light
Robot
Cellular Phone
Remote Controls
Machine Tools/Cutting/ Press
Speech Synthesizer
Infrared and Radar Systems
Missiles
Laser Guided Bombs
Airplane controller
PLC
Gasoline Station
Space Craft/Station
Submarine Control
Airplane/Aero Industry
Refrigeration and Aircon
control
Microprocessor Manufacturing
New Developments
What is superscalar
architecture?
Superscalar architecture is a method of parallel
computing used in many processors. In a
superscalar computer, the central processing unit
(CPU) manages multiple instruction pipelines to
execute several instructions concurrently during a
clock cycle. This is achieved by feeding the
different pipelines through a number of execution
units within the processor. To successfully
implement a superscalar architecture, the CPU's
instruction fetching mechanism must intelligently
retrieve and delegate instructions. Otherwise,
Multithreading
Multithreading is designed to
improve performance by performing
work using one or more threads at
the same time.
multithreading is the ability of a central
processing unit (CPU) or a single core in a multicore processor to execute multiple processes or
threads concurrently, appropriately supported by
the operating system. This approach differs from
multiprocessing, as with multithreading the
processes and threads have to share the
resources of a single or multiple cores: the
Where
multiprocessing
systems
include multiple complete processing
units,
multithreading
aims
to
increase utilization of a single core
by using thread-level as well as
instruction-level parallelism. As the
two techniques are complementary,
they are sometimes combined in
systems with multiple multithreading
CPUs and in CPUs with multiple
PREFETCHING
instruction prefetch is a technique used in
central processor units to speed up the
execution of a program by reducing wait
states.
Prefetching occurs when a processor
requests an instruction or data block from
main memory before it is actually needed.
Once the block comes back from memory,
it is placed in a cache. When the
instruction/data block is actually needed, it
can be accessed much more quickly from
the cache than if it had to make a request
from memory. Thus, prefetching hides
PIPELINE
A pipeline is a set of data processing
elements connected in series, where
the output of one element is the
input of the next one. The elements
of a pipeline are often executed in
parallel or in time-sliced fashion; in
that case, some amount of buffer
storage is often inserted between
elements.
HTTP pipelining, where multiple
A
multi-core
processor
implements
multiprocessing in a single physical
package. Designers may couple cores in a
multi-core device tightly or loosely.
For example, cores may or may not share
caches, and they may implement message
passing or shared memory inter-core
communication methods.
Common
network
topologies
to
interconnect cores include bus, ring, twodimensional mesh, and crossbar.
Homogeneous multi-core systems include
only identical cores, heterogeneous multicore systems have cores that are not
Nehalem Microarchitecture
Nehalem (pronounced /nhelm/[1]) is
the codename for an Intel processor
microarchitecture, successor to the Core
microarchitecture. Nehalem processors
use the 45 nm process. A preview
system with two Nehalem processors
was shown at Intel Developer Forum in
2007. The first processor released with
the Nehalem architecture was the
desktop Core i7,.which was released in
November 2008.
Haswell Microarchitecture
Haswell will be the first processor to be designed from
the ground up to fully optimize the power savings
and performance benefits from the move to 3D or
tri-gate transistors on the improved 22 nm process
node.
Performance
Compared to Ivy Bridge (expected):
At least 10% CPU performance increase.[6]
Double the performance of the integrated GPU.
Technology
A 22 nm manufacturing process.
3D tri-gate transistors.
A 14-stage pipeline (since the Core microarchitecture)
Microcontrolle
rs
Microcontroller
Microcontroller
VS
Microprocessor
8 bit Microcontrollers
Motorola -68HC08
Intel -8051
Atmel -AVR
Zilog- Z8
MicrochipTechnology -PIC
Mechatronics and
Microcontrollers
THE END