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# CMOS Analog Design Using

Chapter 5
Current mirrors

Using All-Region

## The basic current mirror

First-order analysis

VDD

VOUT

IIN

IOUT

M1

M2

M1=M2

W
I D I S i f ir G (VG ,VS ) G (VG ,VD )
L
Both M1 & M2 in saturation

G (VG , VD ) 0

1:1

## Since M1 & M2 are identical with same

gate, source and bulk voltages:
M1: iv converter
M2: vi converter

I OUT I IN

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VDD

VDD
IIN

IIN

IOUT

W/L

W/L

VDD
IIN

IOUT

W/L

W/L
W/L
1:2

W/L

IOUT

2W/L

W/L
1:2

1/2:1
Why not?

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## Error due to difference in drain voltages

I D I S f VG VT ,VS 1 VD VD VDsat

VDD

iout I S f VG VT , VS 1 vout

iin
I S f VG VT ,VS 1 vin

iin
iout
M1

+
v
-

+
-

M2

vout

iout iin
v v
vout vin out in
iin
VA

1:1
The linear variation of the drain current
with the drain voltage is a crude
approximation. =1/VA , VA is the Early

ID

-VA

VD

channel length.

Using All-Region

## Error due to mismatch - 1

I D I S f VG VT ,VS 1 VD VD VDsat
VDD
iin
iout
M1

+
vin
-

+
v =v
- out in

M2

1:1

## Error due to mismatch is negligible.

The mismatch can be calculated
either using Pelgroms model

or

N oi
N *2

AVT 0

2 ID
AVT 0
2 2

ISH

I D2
WL
n

I2D
I D2

2

2

1 i f 1

1 i f
2 N oi 1
2

ln
*2
AISH
WL N i f ir 1 ir

Using All-Region

## Dependence of current matching on inversion level in linear and saturation regions

(|VDS| = 20 mV and |VDS| = 2 V, respectively, where VDS is the drain-to-source
voltage) for the large, medium-size, and small PMOS transistor arrays.

## CMOS Analog Design

Using All-Region

Frequency response
ii
io

ii

gi

vo

M1

+
v
-

M2

C3

io

vi

i2

gm1+
gds1

C1

gm2vi

gds2

C2

vo

1:A

## C1 Cgs1 Cgb1 Cgs 2 Cgb 2 Cdb1

C1 1 A C gs1 C gb1 Cdb1
I out
A
s

I in
1 s

C1
1 A

g mg1 2 fT

## 1. Model is valid as long as 1<<1;

2. C3 introduces a finite zero in the
transfer function;
3. Yin

vout 0

g m1 s C1 C3

Yout g ds 2 s C2 Cdb 2

## CMOS Analog Design

Using All-Region

Noise analysis
ii2

ac model (capacitive
effects not accounted for)

ii
io2

i12

M1

M2

g mg1

i1

2
2

1:A

iout

g ds1

+
v
-

g mg 2 v

i2

## ii, i1, i2 noise sources associated with input

signal source, M1, and M2, respectively.

Superposition

gm2
io ii i1
i2
g m1

&

2
2
2 g m 2
2
io ii i1

2
g
m1

gm2
A
g m1

## Thermal & flicker noise

CMOS Analog Design
Using All-Region

## Current gain schemes - 1

VDD

Gain=A

ii

Gain=1/(NM)
io==Aii

io==ii/(NM)

......

ii

VDD
ii

io==ii/A

......

..
...
.

.....
.
M

Gain= 1/A
CMOS Analog Design
Using All-Region

I

R
I/4

I/2
2R

2R

R
I/16

I/8
2R

2R

Using All-Region

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## Current gain schemes - 3

C. C. Enz and E. A. Vittoz, CMOS Low-Power Analog Circuit Design, Chapter 1.2 in Emerging
Technologies, R. Cavin and W. Liu (eds.), Tutorial for ISCAS 96.

Using All-Region

11

i
G1

VCM

G2
io G2 / G1 i

Inverting
current mirror

VCM

VDD
i

M1

VCM

VDD

W / L 2
io
i
W
/
L

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M2
VCM

12

VDD
IIN

VOUT

IOUT

## Error VOUT VIN

VIN
M1

M2
1:1

dI OUT
Low output impedance large
dVOUT

## Possible solution: Increase L

Is frequency response acceptable?

t
fT
2
2
2 L

1 if 1

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13

## Cascode current mirror - 2

Basic idea to improve the
performance of the simple current
mirror output voltage follows the
input voltage

## Choosing VDVDSsat1 gives

maximum output swing

current mirror

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14

## Cascode current mirror - 3

iout

VB
VDD

M3

iin
X
M1

+
v
-

M2

1:1
The cascode stage

vout
+
-

## 1. Voltage at node X is (almost) independent

of Vout (as long as M3 operates in saturation).
Output impedance (small-signal analysis):

iin 0 v 0
iout g mg 2v g md 2vx ; iout g ms 3vx g md 3vout
iout
g md 3
g
g md 2
g md 2 md 3
vout
g ms 3 g md 2
g ms 3
Output conductance
of a single transistor

Inverse of
voltage gain

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15

## Self-biased cascode current mirror - 1

Suppose M1M2M3 M4

VDD
+
VCS
_

iin

iout
M4

M3
Y

M1

+
v
-

1:1

M2

## 1. First-order analysis: If M4 operates in

saturation, then VXVY and Iout Iin
vout
+
-

iin 0 v 0;

iout
g
g md 2 md 3
vout
g ms 3

## 3. Note that VDD> VCS+VGS3+VGS1

VCS is the minimum voltage for proper
operation of the current source
4. Note that Vout> VGS1+VDS4,sat for
saturation of M4
5. SBCCM is not a low-voltage current
mirror
CMOS Analog Design
Using All-Region

16

## Self-biased cascode current mirror - 2

Example: 0.35 um CMOS technology,
VT0N=0.55V, n1.3, ISQN=70 nA, W=10 m,
L=1 m
a) Iin=70 A, IS=70x10/1=700 nA

VDD
+
VCS
_

iin

iout
M4

M3
Y

vout
+
-

if=70/0.7=100
VP1
1 i f 2 ln
t

1 i f 1 10.25

## VY 1.3t 10.25 0.550 0.883 V

VP 3 VY
1 100 2 ln 1 100 1
t

M2

M1
1:1

## b) Whats the minimum Vout to

keep M4 in saturation
c) Whats VG3 in a) if VSB3=0?
d) Exercise: Repeat a), b),
and c) for Iin=70 nA
CMOS Analog Design
Using All-Region

17

## Low-voltage cascode current mirror - 1

Saturation of M3:
iout

VB
VDD

M3

iin
X
M2

M1
1:Ai

vout
+
-

## VDS 3 VDS 3, sat

Vout VX VDS 3, sat
To maximize the output voltage swing
minimize VX VX= VDS2,sat + V
VB should be designed accordingly.
Error due to different VDS for M1 & M2

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VDD
Iout
Iin

M3

IB

M4
X

## M2 on the edge of saturation

V t
(I) VS 3 VDS 2 VDSsat 2 V
VDSsat t ( 1 i f 3)
UICM applied to M3, find VG3 such that (I) is
satisfied
UICM applied to M4, find if4 such that VG3 is
obtained
Find a set IB4 & S4 for the value found for if4

M2

M1
1:Ai

Using All-Region

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## Low-voltage cascode current mirror - 3

VDD

VDD

IB

IB5

M5

VP 5 t 1 i f 5 2 ln

M3

M1

1 i f 5 1

VP 4 VS 4 t 1 i f 4 2 ln

VO
IO

M2

+
VDS2
_

## Symmetric low-voltage cascode

current mirror

1 i f 4 1

(II)

V t

VS 4 VDS 2 VDSsat 2 V

M4

(I)

VDSsat t ( 1 i f 3)

(I)=(II)
1 i f 5 1 ln

1 i f 4 3 1 i f 4

I in I B iin

## CMOS Analog Design

Using All-Region

1 ln

1 i f 5 1

if 4

1 i f 4 1

IB
IS 4

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Experimental results - 1

2 m CMOS technology
VT0N0.55 V

## CMOS Analog Design

Using All-Region

21

Experimental results - 2

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22

VDD

VDD
IB

M3

VDD

M6

M8

M1
II

VBias
M4

IO

M2
IB

M5

Using All-Region

M7

23

## Appendix: current mirror distortion - 1

Distortion in CM is mainly generated by VT (doping fluctuations)
mismatch and dependence of the current on the output voltage
VDD

IB1

IIN

M1

IB2+IOUT

M2

I
VT 0
I B
I I
2
B 2 B1 S
IB
IS
I B 2 I B1
1 i f 1 nt

I S
I I
S 2 S1
IS
I S 2 I S 1

if

VT 0 VT 02 VT 01

IB
IS

I I
I I
VP1 VP 2 VT 0

1 B1 IN 1 B 2 OUT
t
nt
I S1
IS 2

## Simple MOS current mirror and symbols

used to analyze distortion. Drain voltages
of M1 and M2 assumed to be equal.

ln

I B1 I IN
1

ln

I S1

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I B 2 I OUT

IS 2

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dI OUT
dI IN

1
0

d 2 I OUT
2
dI IN

d 3 I OUT
3
dI IN

I S
1 VT 0

1
IS
1 i f nt

VT 0
2nt I S

3 VT 0

4 nt I S2

1
1 if

I MO 2
I M VT 0
HD2

IM
8I S nt

1
1 if

I
HD3 MO 3
IM

1 I M

32 I S

Using All-Region

1
1 if

VT 0
nt

1
1 if

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