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INTRODUCTION TO
PROGRAMMABLE
LOGIC
CONTROL
Revision 2
ASSESSMENT
Topic 1
Basic Principle of
Control Technology
PLC
What is CONTROL?
DIN 19226
A Simple View of a Control System
INFORMATION C S SENSORS
O Y P
N S L
T T A
COMMANDS R E ACTUATORS N
O M T
L
Open-loop Control System
N
Closed-loop Control System
L
Xi > Xs C
Xi - Required value
Xi
Xs - Actual value Xs
Xi < Xs
N
Handout section 1.1
L 24 VDC
S1 S1 S2
S2 K1
PLC
K1 K1
N 0V
Hardwire PLC
Comparison
Hardwired control systems Programmable control system
Later, PC was used for Personal Computer and to avoid confusion PLC
for Programmable Controller and PC for a personal computer.
ADVANTAGES OF PLC COMPARED TO HARDWIRE
Speed of operation
Reliability
Documentation
Handout section 1.4
POWER PG/
SUPPLY PC
MEMORY
(EPROM/RAM)
Input Connections
Input card
Converter
Input field voltage to 5V
Devices acceptable by the CPU
Handout section 1.4.1
Detection
Bridge
Signal
Conditioning
Logic Status
Threshold
Light
Decision
Opto-Isolation
Logic
To CPU / Memory
Output Connections
Output card
Converter
5V to field voltage
Output
to drive field devices Devices
Handout section 1.4.2
Logic Status
Logic Light
Opto-Isolation
Switching
Circuitry
Protection
Circuitry
To field wiring
Input / Output Modules
Digital input modules adapt digital signals e.g. from proximity
sensors
Digital output modules convert the internal signal level of PLC into
digital process signals e.g. relays
What is a CPU?
Jump operations
CPU
INTERNAL MEMORY
PROGRAM SUBMODULE
ACCUMULATOR MEMORY (EPROM/
(RAM) EEPROM/
RAM)
TIMERS,
COUNTERS,
Memory SERIAL
INTERFACE
PROCESSOR
PII PIQ
CPU
The CPU reads in input signal states, processes the control program
and controls the outputs.
Restart procedure can be preset and errors can be diagnosed using the
CPUs LEDs.
The overall Reset on the CPU is used to delete the contents of the
RAM.
Program Memory
Program memory
Program memory
Programmable Non-programmable
(Read-write memory)
Non-alterable
Alterable ROM / PROM
EEPROM SUBMODULE
EEPROM submodule can be programmed or erased using a
programmer
RAM SUBMODULE
Can be used in addition to program storage; and used to test a
control program during system startup
Handout section 1.4.5
Backup battery
The backup battery maintains the program and data when the PLC
is switch off
Input Output
devices devices
Handout section 1.6
Operand identifiers:
I - Input
Q - Output
example: example:
A I 0.0 A System_On
= Q 8.0 = System_On
A I0.4 A M_FORW
= Q20.5 = MOTOR_FOR
Call FC18 Call COUNT
Very similar to traditional circuit diagrams, but the current paths are
arranged horizontally instead of vertically
Handout section 1.8.2
I 0.1
& Q 4.0
Inputs are arranged on the left side while outputs on the right
Handout section 1.8.3
Operation;
Describes the function to be carried out (what is to be done)
e.g Binary operations, Digital operations and Organizational operations
Operand;
START FROM HERE
Handout section 1.8.4
OPERATION + OPERAND
Q 4.0
( ) = Q 4.0 = Q 4.0
Handout section 1.9
Program Execution
OB = Organization Block
A I 0.0
A I 0.1
When the PLC is set to run, the = Q 4.0
PLC will look for OB1 only in the :
:
user memory and execute it :
BE
OB1 FC 1
Network 1 Network 1
A I 0.6 A I 0.6
A I 0.7
A I 0.7 = Q 4.2
OB 1
= Q 4.2 Network 2
A I 0.7
Network 2 Network 1
A I 0.5
A I 0.7 JU FC 1 = Q 4.3
A I 0.5 BE
JU FC 4
= Q 4.3
Network 3 BE FC 4
A Q 4.2 Network 1
A I 0.2 A Q 4.2
= Q 5.5 A I 0.2
= Q 5.5
BE BE
Handout section 1.9.3
Program Execution
Input Process Program in Process Output
24 VDC module input image the RAM output image module GND
1 0
I 0.0 A I 0.0
0 Q 4.0
A I 0.1
I 0.1
P = Q 4.0 P
I I 1
O I 0.5
I O I 0.7
Q Q 4.3
1
I 0.5 = Q 4.3
BE:
1
I 0.7
Updated by the
program logic during
program execution
OB1 PIQ
The contents of PIQ
are transferred to the
output module at the
end of OB1
Copy PIQ to Output Module
Handout section 1.9.4
BLOCK TYPES
ORGANISATION BLOCKS (OB) Interface between the operating system and the
user program
DATA BLOCKS (DB) Are data areas of the user program in which user data are
managed in a structured manner
FUNCTION BLOCKS (FB) - FBs are blocks with a memory which you can
program yourself
INSTANCE DATA BLOCKS (DB) - Instance DBs are associated with the block
when an FB/SFB is called. They are created automatically during compilation
Block Nesting Depth
FC 7
FC 4 A I ....
FC 1 ..
OB1 JU FC 7 ..
JU FC4 .. ..
JU FC 1 .. ... BE
.. ... BE
... BE
..
BE
Handout section 1.9.5
I (Input)
Interface from the process to the programmable controller
Q (Output)
Interface from programmable controller to the process
M (Memory/Flag)
Memory for intermediate results of binary operations
T (Timer)
Memory for implementing timers
C (Counter)
Memory for implementing counters
Handout section 1.9.6
Topic 3
Programming Basic
Functions
Handout section 3.1
Assignment Lists
Program Structure
Problem Description
it consists of process schematic, a short description of the task
definition, and a list of the sensors and actuators
Assignment List
the sensors and actuators are allocated to the parameters of the
programmable controller
it contains a short functional description as well as the device
identifier
The Stages of Project Planning
Program Structure
it determines the order in which the LAD, FBD or STL diagram to
be drafted
LAD
I 0.0 I 0.1 Q 4.0
( )
FBD STL
I 0.0 A I 0.0
I 0.1
& Q 4.0
A I 0.1
= Q 4.0
Handout section 3.3
OR Operation
LAD
I 0.0 Q 4.0
( )
I 0.1
FBD STL
I 0.0 O I 0.0
>= 1 Q 4.0 O I 0. 1
I 0.1 = Q 4.0
Handout section 3.4
Latching Output
S3 K2 S1 K1
S4 S2
K2 K1
RS Memory Function
S3 K2 S2
R
S4
= S1 K1
K2 S Q ( )
S1 K1 S3
S
S2
= S4 K2
K1 R Q ( )
LAD
I 0.0 I 0.1 Q 4.0
( ) the PLC registers in the PIQ
that Q 4.0 is 1
I 0.2 I 0.3 Q 4.0
the PLC registers in the PIQ
( ) that Q 4.0 is 0
so, Q 4.0 = 0
When I0.2 and I0.3 Are Activated...
LAD
I 0.0 I 0.1 Q 4.0
( ) the PLC registers in the PIQ
that Q 4.0 is 0
I 0.2 I 0.3 Q 4.0
the PLC registers in the PIQ
( ) that Q 4.0 is 1
so, Q 4.0 = 0
When I0.4 and I0.5 Are Activated...
LAD
I 0.0 I 0.1 Q 4.0
( ) the PLC registers in the PIQ
that Q 4.0 is 0
I 0.2 I 0.3 Q 4.0
the PLC registers in the PIQ
( ) that Q 4.0 is 0
M 100.2
Result of Logic Operation (RLO)
Topic 4
Numerical Systems and
Data Formats
Handout section 4.1
Characteristics:
They are used to perform operations on a whole byte or word in
memory
They are unconditional operations i.e. They are performed by the
processor in each cycle
Functions:
Exchange information between various operand areas
Prepare times and counts for further processing
Load constants for program processing
Load Operation
L IB 0
ACCUM 2 ACCUM 1 L IB 1
Byte b Byte a 0 IB 0
IB 1
0 IB 0 0 IB 1
Information from PII
Transfer Operation
T QB 0
ACCUM 2 ACCUM 1
Byte a QB 0
Topic 5
Timer Operations
Handout section 5.0
Return Operations
BE (Block End)
the return operation is performed unconditionally
it is always the last statement in the block
Topic 6
Counter Operations
Handout section 6.0
Counter
Counter Operations
CU - count up
CD - count down
S - set counter to the count value (CV)
CV - the count value
R - reset the counter (count value = 0)
BI - counter output as binary number
DE - counter output as BCD number
Q - counter status
Q = 0 when count value = 0
Q = 1 when count value > 1
Handout section 6.2
Timing Diagram
Counter Input
Handout section 6.3
Counter Output
Handout section 6.4
Comparator
Types of comparison:
Comparator