FPGA-Based Digital

Design
Dr. K. Shyamala
Department of CSE
prkshyamala@gmail.com

02/17/17 Dept of CSE 1

 OUTLINE

Introduction
FPGA Design Flow
Issues in FPGA based Designs
Research Trends in FPGAs

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 Digital Logic

Logic Gates

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 Digital Logic

Logic Gates

Transistor Switches

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 Digital Logic

Logic Gates

Transistor Switches

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 Introduction: Digital Logic

Digital Logic Function Product AND (&)

Sum OR (|)

3 Inputs

SUM of PRODUCTS
Black Box Truth Table
(Look Up Table LUT)

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 Introduction: Digital Logic

Digital Logic Function Product AND (&)

Sum OR (|)

3 Inputs

SUM of PRODUCTS
Black Box Truth Table
(Look Up Table LUT)

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 Introduction: Digital Logic

Digital Logic Function Product AND (&)

Sum OR (|)

3 Inputs

SUM of PRODUCTS
Black Box Truth Table
(Look Up Table LUT)

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 Introduction: Programmable Logic
Programmable digital integrated circuit

Desired functionality is implemented by configuring on-chip

logic blocks and interconnections

Advantages (compared to an ASIC):

Low development costs

Short development cycle

Device can (usually) be reprogrammed

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 Introduction: Programmable Logic

Programmable Logic Devices:

Read-Only Memorys (ROM)

Programmable Logic Arrays (PLA)

Programmable Array Logic (PAL)

Complex Programmable Logic Devices (CPLD)

Field Programmable Gate Arrays (FPGA), and

Mask-Programmable Gate Arrays (MPGA).

 Programmable Logic Devices
PLDs have
a fixed architecture

Functionality is programmed for a specific application

Programming is done by:

Manufacturer - mask-programmable logic devices (MPLD)

End-User field-programmable logic devices (FPLD).

Three basic characteristics distinguish PLDs from each other:

1. An architecture of identical basic functional units

2. A programmable interconnection fabric, and

3. A programming technology.
 Programmable Logic Devices
The first type of PLDs considered has the AND-OR plane structure.
This type of architecture is used to implement ROMs, PLAs, and PALs.
It implements Boolean expressions in Sum of Products (SOP) form:

AND plane forms product terms selectively from the inputs, and

OR plane forms outputs from sums of selected product terms.

A programmable interconnect fabric joins the two planes, so that the outputs implement sum-of-product expressions of
the inputs.
 Programmable Logic Devices
How a plane can be programmed determines the particular type of PLD

that is implemented by the overall structure.

Product Terms

Inputs AND Plane OR Plane Outputs

AND-OR plane structure of a programmable logic device

 Programmable Logic Devices (PLDs)
Inputs

ANDs Un-programmed State

SUM of PRODUCTS
(Re-)Programmable Links Planes of
ANDs, ORs
Reconfigurable
ORs
GLUE LOGIC
Outputs

Logic Functions

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 Programmable Logic Devices (PLDs)
Inputs

ANDs Un-programmed State

SUM of PRODUCTS
(Re-)Programmable Links Planes of
ANDs, ORs
Reconfigurable
ORs
GLUE LOGIC
Outputs

Logic Functions

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 Programmable Logic Devices (PLDs)
Inputs

ANDs Un-programmed State

SUM of PRODUCTS
(Re-)Programmable Links Planes of
ANDs, ORs
Reconfigurable
ORs
GLUE LOGIC
Outputs

Logic Functions

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 Programmable Logic Devices (PLDs)
Inputs

ANDs Un-programmed State

SUM of PRODUCTS
(Re-)Programmable Links Planes of
ANDs, ORs
Reconfigurable
ORs
GLUE LOGIC
Outputs

Logic Functions

Sums

Programmed PLD
Product Terms

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 Programmable Logic Devices (PLDs)

Logic Functions

Programmed PLD

Sums

Product Terms

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 Programmable Logic Devices (PLDs)

Logic Functions

x x x
Programmed PLD

x x
Sums

Product Terms

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 Programmable Logic Devices (PLDs)
Logic Functions
GLUE LOGIC

x x x x
Programmed PLD

x x x
Sums

Product Terms

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 Programmable Logic Devices (PLDs)

Can implement combinational or sequential logic

Select
A B C Enable

f1

Flip-flop
MUX
D Q

Clock

AND plane
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 Complex PLDs
CPLDs
Feedback Outputs
Programmable PLD Blocks
Programmable Interconnects
Electrically Erasable links

CPLD Architecture

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 CPLD Structure
Integration of several PLD blocks with a
programmable interconnect on a single chip
I/O Block

I/O Block
PLD PLD

Block Block

Interconnection Matrix
I/O Block

I/O Block
PLD PLD

Block Block
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 Implementing Digital Circuits

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Gate Arrays

Macro Cells FPGA's
Compiled Cells Structured ASICs

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 Introduction..Summary
Technologies available for implementing digital circuits range
from:
Standard Integrated Circuits (ICs) used in low-density/low-
performance applications,
To Cell-based and full-custom ICs for high-density/high-performance
circuits.
Standard ICs:
Can be manufactured cheaply,
Implement very limited, basic functionality at low levels of
integration.
Customized ICs
Implement specialized functionality with a high level of integration
expense of their development and production.

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 CPLDs vs. FPGAs
CPLD architecture:
Small number of large
PLDs on a single chip
Programmable interconnect
between PLDs
 CPLDs vs. FPGAs
FPGA architecture:

Much larger number of

smaller programmable logic
blocks.
Embedded in a sea of gates
and large number
of programmable interconnect.
 How can we make a
programmable logic?

One time programmable

Fuses (destroy internal links with current)
Anti-fuses (grow internal links)
PROM
Reprogrammable
EPROM
EEPROM
Flash
SRAM - volatile
 Introduction to FPGAs
Categories of field-programmable
devices:

Fuse-based (program-once) FPGAs

Non-volatile EPROM based FPGAs
RAM based FPGAs

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Introduction to FPGAs..

Configurable
Logic
Blocks

I/O
Block RAMs

Block RAMs
Blocks

Block
RAMs

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 Introduction to FPGAs..
FPGA programmable device to implement any digital
circuit
Look Up Tables (LUTs), I/O Blocks and Interconnections

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 Introduction to FPGAs

Logic Blocks
- used to implement
logic
- lookup tables and
flip-flops

Altera: LABs
Xilinx: CLBs

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 Introduction to FPGAs

I/O Blocks
- interface off-chip
- can usually support
many I/O Standards

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 Introduction to FPGAs
L o g ic B lo c k
C o n n e c tio n
B lo c k

S w itc h B lo c k

R o u tin g T r a c k
(H o r iz o n ta l)

R o u tin g C h a n n e l
{
(V e r tic a l)

T IL E
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 Logic Blocks
Choices
Fine Grained
Basic gates: NAND, NOR, XOR, FF etc.
Medium Grained
Lookup Tables
Coarse Grained
Multi-input, Multi-output blocks (e.g., PLAs)
Configurability
SRAM cells

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Example:LUT
 Whats Inside an FPGA?

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 Reconfigurable Logic:

Connect Logic
Blocks using
Fixed Metal
Tracks and
Programmable
Switches

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 Reconfigurable Logic:

Connect Logic
Blocks using
Fixed Metal
Tracks and
Programmable
Switches

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Advantages of FPGAs:
"Instant Manufacturability": reduces time to market
Cheaper for small volumes because you dont need to pay
for fabrication

Disadvantages of FPGAs:
Slower than custom or standard cell based chips
Cannot get as much circuitry on a single chip
Today: ~ 1M gates is the best you can do
~ 200 MHz is about as fast as you can get
For large volumes, it can be more expensive than gate
arrays and custom chips

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 Other FPGA Advantages

Manufacturing cycle for ASIC is very costly,

lengthy and engages lots of manpower
Mistakes not detected at design time have
large impact on development time and cost
FPGAs are perfect for rapid prototyping of
digital circuits
Easy upgrades like in case of software
Unique applications
reconfigurable computing
 Major FPGA Vendors

SRAM-based FPGAs
Xilinx, Inc. Share over 60% of the market
Altera Corp.
Atmel
Lattice Semiconductor

Flash & antifuse FPGAs

Actel Corp.
Quick Logic Corp.
 FPGA Design Flow

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 Introduction to Design flow
ASIC design
Flow

The given design description

is converted into

1. Optimized gate-level netlist

2. Technology-dependent
netlist
( gate-level netlist using
standard cell libraries)
3. Physical layout of the
design.
FPGA design Flow
 FPGA design Flow..
Various Steps involved in the design flow are:

The given design description is converted into

1. Optimized gate-level netlist

2. Technology-dependent netlist (Look Up Tables)
3. Bit stream is used to program the given FPGA device.

Estimation of Power, Area and Timing are typically done at

post-synthesis/ pre-layout stage of the design flow.
FPGA design Flow..

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Implementing larger functions
using LUTs
 Logic Synthesis

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 Compilation and optimization:
Synthesis
All non-synthesizable data types and
operations synthesizable code
Translated into a set of Boolean equations
Then minimized (Technology-independent
optimization)
Technology mapping:
Assign functional modules to library elements.
On FPGAs:
Mapping control logic and datapath to LUTs and BLEs

Mapping optimized datapath to on-

chip dedicated circuit structures
(e.g. on-chip multipliers, adders
with dedicated carry-chains,
embedded memory blocks)
Technology-dependent optimization

50
 Logic Synthesis
Result:
Netlist: a list of components and their
interconnections.
Netlist Formats:
EDIF (Electronic Design Interchange
Format).
Vendor specific formats.
Example: XNF (Xilinx Netlist Format)

51
CLBs can be implemented by standard
cell library also where S={set of
cells}
Each cell consists of logic elements
2 input NAND gates
3 and 2 input NAND gates
NOT
Buffers
AOI(AND OR Invert gates)
Mapping a gate network to
LUTs
Mapping a gate network to
3LUTs
Mapping same network to
4LUTs
 Physical Design: Placement & Routing
Place:
Assign locations to the components
Estimation of total wire length
Rectilinear

Route:
Provide communication paths to the
interconnections.
Optimization problems: some cost must be minimized

Important factors:
Clock frequency
Power Consumption
Routing congestion

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 FPGA Placement & Routing

57
 FPGA Design Flow

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 Configuration Bitstream
Bitstream:

LUT contents,

Multiplexer control lines,

Interconnections,

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 FPGA Design Flow...

The given design description

is converted into

1. Optimized gate-level
netlist
2. Technology-dependent
netlist
(Look Up Tables)
3. Bit stream is used to
program
the given FPGA device.

Estimation of Power, Area and

Timing are typically done at
Post synthesis/ pre-layout stage
of the design flow.
 Design Flows

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 Design Flows

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 Design Flows

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 Design Flows

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 Design Flows

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 Implementing Logic Circuits
Design Capture Behavioral

HDL
HDL
Pre-Layout
Pre-Layout
Simulation Structural
Design

Simulation Logic
LogicSynthesis
Synthesis
Iteration

Floorplanning
Floorplanning
Post-Layout
Post-Layout
Simulation
Simulation Placement
Placement Physical

Circuit
CircuitExtraction
Extraction Routing
Routing

Tape-out

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 Designing Logic with

FPGAs
High level Description of Logic Design
Hardware Description Language (Textual)

Compile (Synthesis) into NETLIST.

Boolean Logic Gates.

Target FPGA Device

Mapping
Routing
Bit File for FPGA

Commercial CAD Tools Design Flow

(Complex & Expensive)

Logic Simulation
 Field Programmable Gate Arrays
(FPGA)
Large Complex Functions
Re-Programmability, Flexibility.

Massively Parallel Architecture

Processing many channels simultaneously of MicroProcessor

Fast Turnaround Designs

Standard IC Manufacturing Processes.
Mass produced. Inexpensive.
Many variants. Sizes. Features.
 Xilinx

Primary products: FPGAs and the associated

CAD software

Programmable
Logic Devices ISE Alliance and Foundation
Series Design Software
 Xilinx FPGA Families
Old families
XC3000, XC4000, XC5200
High-performance families
Virtex
Virtex-E, Virtex-EM
Virtex-II, Virtex-II PRO
Low Cost Family
Spartan/XL derived from XC4000
Spartan-II derived from Virtex
Spartan-IIE derived from Virtex-E
Spartan-3
Basic Spartan-II FPGA Block
Diagram
 CLB Structure
COUT COUT

YB YB
G4 Y G4 Y
G3 Look-Up Carry D
S
G3 Look-Up Carry D
S
Q Q
G2 Table O & G2 Table O &
CK CK
G1 Control G1 Control
Logic EC Logic EC
R R
F5IN F5IN
BY BY
SR SR
XB XB
X S X S
F4 Look-Up Carry D Q
F4 Look-Up Carry D Q
F3 Table O F3 Table O
F2
& F2
&
CK CK
F1 Control F1 Control
Logic EC Logic EC
R R

CIN CIN
CLK CLK
CE SLICE CE SLICE

Each slice has 2 LUT-FF pairs with associated carry logic

Two 3-state buffers (BUFT) associated with each CLB,
accessible by all CLB outputs
 CLB Slice Structure

Each slice contains two sets of the

following:
Four-input LUT
Any 4-input logic function,
16-bit x 1 sync RAM
16-bit shift register
Carry & Control
Fast arithmetic logic
Multiplier logic
Multiplexer logic
Storage element
Latch or flip-flop
Set and reset
True or inverted inputs
Sync. or async. control
 LUT (Look-Up Table) Functionality
x1 Look-Up tables are
x2
y primary elements for
x1 x2 x3 x4 y x3 LUT x1 x2 x3 x4 y
x4
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
1
logic implementation
0 0 1 0 1 0 0 1 0 0
0 0 1 1 1 0 0 1 1 0 Each LUT can
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
implement any function
0 1 1 0 1 0 1 1 0 0 of 4 inputs
0 1 1 1 1 0 1 1 1 1
1 0 0 0 1 1 0 0 0 0
1 0 0 1 1 1 0 0 1 1
1 0 1 0 1 1 0 1 0 0
1 0 1 1 1 1 0 1 1 0
1 1 0 0 0 1 1 0 0 1
1 1 0 1 0 1 1 0 1 1
1 1 1 0 0 x1 x2 x3 x4 1 1 1 0 0
1 1 1 1 0 1 1 1 1 0

x1 x2

y
 5-Input Functions implemented
using two LUTs

One CLB Slice can implement any function of 5 inputs

Logic function is partitioned between two LUTs
F5 multiplexer selects LUT
LUT
A4
ROM
D
A3 RAM
A2
A1
WS DI F5
0
F5
1 X
WS DI GXOR
F4 A4 G
D
F3 A3
F2 A2 LUT
ROM
F1 A1
RAM

BX nBX
BX
1
0
 5-Input Functions implemented
using two LUTs
X5 X4 X3 X2 X1 Y
0 0 0 0 0 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 1 0 LUT
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 1 0 0
0 1 0 1 1 1 OUT
0 1 1 0 0 1
0 1 1 0 1 1
0 1 1 1 0 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 0 1 1 0
1 0 1 0 0 0
1 0 1 0 1 0
1 0 1 1 0 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 1 1
LUT
1 1 0 1 0 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 1 0
FPGA Nomenclature
 Research Issues
Any digital systems are either realized as Application
Specific Integrated Circuits (ASICs) or Field
programmable Gate Arrays (FPGAs).

Field programmable Gate Array (FPGA) consist of

Programmable logic blocks, Programmable Input and
Output blocks and Programmable interconnections.

The infield reconfigurability of the FPGAs make them highly

suitable for applications like space compared to ASICs
Issues: power, area and timing optimization for designs
configured onto FPGAs.
 Research Issues...
Early estimation of power, area and
timing is crucial.
These three parameters are to be
addressed together to design an
efficient power-aware designs.
Early estimation of area and timing of
the designs are easier compared to
estimating power consumption
Major Power components of the circuit
Static - easy to estimate
Dynamic - difficult to estimate
 Research Trends/Issues
Technology Mapping Issues
Mapping algorithms to minimize
Area
Power
Delay
Power Optimization Issues
Power Estimation Technique
Peak Dynamic Power Estimation
Testing and Validation Issues
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Contribution of the work

Estimation to be
done at this stage
 Summary
Introduction to programming logic
FPGA implementation of digital
circuits
FPGA design flow and issues

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 Thank You

02/17/17 Dept of CSE 83