Introduction to

CMOS VLSI
Design

Lecture 15:
Nonideal Transistors
David Harris

Harvey Mudd College

Spring 2004
 Outline
Transistor I-V Review
Nonideal Transistor Behavior
Velocity Saturation
Channel Length Modulation
Body Effect
Leakage
Temperature Sensitivity
Process and Environmental Variations
Process Corners

CMOS VLSI Design

15: Nonideal Transistors
Slide 2
 Ideal Transistor I-V
Shockley 1st order transistor models

0 Vgs Vt cutoff


I ds Vgs Vt ds Vds Vds Vdsat
V
linear
2


Vgs Vt
2
Vds Vdsat saturation
2
CMOS VLSI Design
15: Nonideal Transistors
Slide 3
 Ideal nMOS I-V Plot
180 nm TSMC process

Ideal Models Ids (A)

400
= 155(W/L) A/V2
Vgs = 1.8
Vt = 0.4 V 300

VDD = 1.8 V 200

Vgs = 1.5

Vgs = 1.2
100
Vgs = 0.9
Vgs = 0.6
0 Vds
0 0.3 0.6 0.9 1.2 1.5 1.8

CMOS VLSI Design

15: Nonideal Transistors
Slide 4
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
I (A)
What differs? ds

250 Vgs = 1.8

200
Vgs = 1.5

150
Vgs = 1.2
100
Vgs = 0.9
50
Vgs = 0.6
0
0 0.3 0.6 0.9 1.2 1.5
Vds

CMOS VLSI Design

15: Nonideal Transistors
Slide 5
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
I (A)
What differs? ds

250 Vgs = 1.8

Less ON current
200
No square law Vgs = 1.5

150
Current increases Vgs = 1.2
100
in saturation Vgs = 0.9
50
Vgs = 0.6
0
0 0.3 0.6 0.9 1.2 1.5
Vds

CMOS VLSI Design

15: Nonideal Transistors
Slide 6
 Velocity Saturation
We assumed carrier velocity is proportional to E-field
v = Elat = Vds/L
At high fields, this ceases to be true
Carriers scatter off atoms
sat

Velocity reaches vsat

Electrons: 6-10 x 106 cm/s

Holes: 4-8 x 106 cm/s sat /2

Better model slope =

Elat
v vsat Esat 0
Elat 0 Esat 2Esat 3Esat

1 Elat

Esat
CMOS VLSI Design
15: Nonideal Transistors
Slide 7
 Vel Sat I-V Effects
Ideal transistor ON current increases with VDD2
W Vgs Vt
2

Vgs Vt
2
I ds Cox
L 2 2

Velocity-saturated ON current increases with VDD

I ds CoxW Vgs Vt vmax

Real transistors are partially velocity saturated

Approximate with -power law model
Ids VDD
1 < < 2 determined empirically
CMOS VLSI Design
15: Nonideal Transistors
Slide 8
 -Power Model
0 Vgs Vt cutoff
Pc Vgs Vt

I dsat
V
2
I ds I dsat ds Vds Vdsat linear
Vdsat

Vdsat Pv Vgs Vt
/2
I dsat Vds Vdsat saturation

Ids (A) Simulated

400 -law
Shockley

300
Vgs = 1.8

200
Vgs = 1.5

100 Vgs = 1.2

Vgs = 0.9
0 Vgs = 0.6
0 0.3 0.6 0.9 1.2 1.5 1.8 V
ds

CMOS VLSI Design

15: Nonideal Transistors
Slide 9
Channel Length Modulation
Reverse-biased p-n junctions form a depletion region
Region between n and p with no carriers
Width of depletion Ld region grows with reverse bias
GND V V DD DD

Leff = L Ld Source Gate Drain

Depletion Region
Shorter Leff gives more current Width: L d

Ids increases with Vds n+

L
n+
Leff
Even in saturation p GND bulk Si

CMOS VLSI Design

15: Nonideal Transistors
Slide 10
 Chan Length Mod I-V
Ids (A)

400

I ds Vgs Vt 1 Vds
2
Vgs = 1.8

2 300

Vgs = 1.5
200

Vgs = 1.2
100
Vgs = 0.9
Vgs = 0.6
0
0 0.3 0.6 0.9 1.2 1.5 1.8 Vds

= channel length modulation coefficient

not feature size
Empirically fit to I-V characteristics
CMOS VLSI Design
15: Nonideal Transistors
Slide 11
 Body Effect
Vt: gate voltage necessary to invert channel
Increases if source voltage increases because
source is connected to the channel
Increase in Vt with Vs is called the body effect

CMOS VLSI Design

15: Nonideal Transistors
Slide 12
 Body Effect Model
Vt Vt 0 s Vsb s
s = surface potential at threshold
NA
s 2vT ln
ni
Depends on doping level NA
And intrinsic carrier concentration ni
= body effect coefficient
t 2q si N A
ox 2q si N A
ox Cox

CMOS VLSI Design

15: Nonideal Transistors
Slide 13
OFF Transistor Behavior
What about current in cutoff?
Simulated results I ds
Saturation Vds = 1.8
What differs? 1 mA
Sub- Region
100 A
threshold
Current doesnt go 10 A Region
1 A
to 0 in cutoff 100 nA
10 nA
Sub-
1 nA threshold
100 pA Slope
10 pA Vt

0 0.3 0.6 0.9 1.2 1.5 1.8

Vgs

CMOS VLSI Design

15: Nonideal Transistors
Slide 14
 Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF
Junction leakage
Reverse-biased PN junction diode current
Gate leakage
Tunneling through ultrathin gate dielectric

Subthreshold leakage is the biggest source in

modern transistors

CMOS VLSI Design

15: Nonideal Transistors
Slide 15
 Subthreshold Leakage
Subthreshold leakage exponential with Vgs
Vgs Vt

Vds

I ds I ds 0e nvT
1 e
vT
I ds 0 vT2 e1.8

n is process dependent, typically 1.4-1.5

CMOS VLSI Design

15: Nonideal Transistors
Slide 16
 DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt

Vt Vt Vds
VVV
ttds

High drain voltage causes subthreshold leakage

to ________.

CMOS VLSI Design

15: Nonideal Transistors
Slide 17
 DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt

Vt Vt Vds
VVV
ttds

High drain voltage causes subthreshold leakage

to increase.

CMOS VLSI Design

15: Nonideal Transistors
Slide 18
 Junction Leakage
Reverse-biased p-n junctions have some leakage
VD

ID IS e vT
1


Is depends on doping levels
And area and perimeter of diffusion regions
Typically < 1 fA/m2

p+ n+ n+ p+ p+ n+
n well
p substrate

CMOS VLSI Design

15: Nonideal Transistors
Slide 19
 Gate Leakage
Carriers may tunnel thorough very thin gate oxides
Predicted tunneling current (from [Song01])
109
tox
VDD trend 0.6 nm
106
0.8 nm

JG (A/cm )
1.0 nm
103

2
1.2 nm

100 1.5 nm

1.9 nm
10-3

10-6

10-9

0 0.3 0.6 0.9 1.2 1.5 1.8

VDD
Negligible for older processes
May soon be critically important
CMOS VLSI Design
15: Nonideal Transistors
Slide 20
Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces Vt
ION ___________ with temperature
IOFF ___________ with temperature

CMOS VLSI Design

15: Nonideal Transistors
Slide 21
Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces Vt
ION decreases with temperature
IOFF increases with temperature

I ds

increasing
temperature

Vgs

CMOS VLSI Design

15: Nonideal Transistors
Slide 22
 So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for
Supply voltage choice
Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation

CMOS VLSI Design

15: Nonideal Transistors
Slide 23
 Parameter Variation
Transistors have uncertainty in parameters
Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values

fast
Fast (F) SF
FF

Leff: ______

pMOS
TT

Vt: ______
FS

tox: ______ SS

slow
Slow (S): opposite slow
nMOS
fast

Not all parameters are independent

for nMOS and pMOS
CMOS VLSI Design
15: Nonideal Transistors
Slide 24
 Parameter Variation
Transistors have uncertainty in parameters
Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values

fast
Fast (F) SF
FF

Leff: short

pMOS
TT

Vt: low
FS

tox: thin SS

slow
Slow (S): opposite slow
nMOS
fast

Not all parameters are independent

for nMOS and pMOS
CMOS VLSI Design
15: Nonideal Transistors
Slide 25
Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: ____
T: ____

Corner Voltage Temperature

F
T 1.8 70 C
S

CMOS VLSI Design

15: Nonideal Transistors
Slide 26
Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: high
T: low

Corner Voltage Temperature

F 1.98 0C
T 1.8 70 C
S 1.62 125 C

CMOS VLSI Design

15: Nonideal Transistors
Slide 27
 Process Corners
Process corners describe worst case variations
If a design works in all corners, it will probably
work for any variation.
Describe corner with four letters (T, F, S)
nMOS speed
pMOS speed
Voltage
Temperature

CMOS VLSI Design

15: Nonideal Transistors
Slide 28
 Important Corners
Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time

Power

Subthrehold
leakage
Pseudo-nMOS

CMOS VLSI Design

15: Nonideal Transistors
Slide 29
 Important Corners
Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthrehold F F F S
leakage
Pseudo-nMOS S F ? ?

CMOS VLSI Design

15: Nonideal Transistors
Slide 30