Vous êtes sur la page 1sur 19

Pipelining

Lecture 2

By K. Santle Camilus
Department of Computer Science and
Engineering

Based on the Book Computer


Organization by Carl Hamacher et al.,
Fifth Edition
Roadmap of todays
presentation
Instruction Hazard
Influence on data set
Superscalar operation
Review of Pipelining-
Lecture 1
Instruction Hazard
Solution to Cache
misses(1/2)
Solution to cache
misses(2/2)
Branch Affecting
pipelining
Conditional Branches
Loop Shift_left R1
Decrement R2
Branch=0 Loop
Next Add R1, R3

Program Loop

Loop Decrement R2
Branch=0 Loop
Shift_left R1
Next Add R1, R3

Reordered Instruction for a delayed branch


Branch Prediction
Attempt to predict whether or not a particular
branch will be taken.
Types
1. Static branch prediction
2. Dynamic branch prediction

Static branch prediction:


The branch prediction decision is always the
same every time a given instruction is
executed.
Any example using any logic of
branch??????
Dynamic The prediction decision may
change depending on
Branch execution history.
Prediction
Influence on instruction sets
Two issues to be considered while
designing instruction sets
1. Side effects
2. Complex address modes which causes delay

Complex addressing modes that


involves several access to the
memory do not necessarily lead to
faster execution.
Equivalent operations using complex
and simple addressing modes
Features of instruction sets in
modern computers
Access to operand does not require
more than one access to memory

Only load and store instructions


access memory

Addressing modes used do not have


side effects
Superscalar operation
The maximum throughput of a
pipelined processor is ?????? per
clock cycle.
If instruction throughput of an
processor is more than ???
instruction per clock cycle-
Superscalar Processor.
An example-superscalar
processor
Out-of-Order Execution issues in Superscalar
operation
- Imprecise exceptions
- Precise exceptions
Execution Completion
Conclusion
Two features have been introduced
1. Pipelining operation
2. Superscalar operation

Potential performance can be realized


by paying attention to
1. Instruction set of the processor
2. The design of the pipeline hardware
3. The design of the associated compiler
For future clarification,
contact
camilus@nitc.ac.in