Chapter 5

Sequential Circuits: Flip-Flops and

Counter

By Taweesak Reungpeerakul

241-208 CH7 1
 Contents
Introduction
Latches
Edge-Triggered Flip-Flops (ET-FFs)
Operating Characteristics and Application
Asynchronous Counter
Synchronous Counter
Cascaded Counters
Counter Decoding
Counter Applications

Conclusions

241-208 CH7 2
 Contents
Basic Shift Register Functions
Serial In/Serial Out Shift Registers
Serial In/Parallel Out Shift Registers
Parallel In/Serial Out Shift Registers
Parallel Out/Parallel Out Shift Registers
Bidirectional Shift Registers
Shift Register Counters
Shift Register Applications
Conclusions

241-208 CH7 3
 Introduction
Well, what u learned before is just one class of digital cir

In fact we can classify into two main classes :-

Output can depend on the
past and present inputs/output

Output depends on the present input.

241-208 CH7 4
 Introduction (cont.)
Synchronous VS Asynchronous

All state transitions are State transitions occur independentl

controlled by a common clock of any clock
Changes in all variables occur Changes in all variables do not
concurrently necessarily occur concurrently

241-208 CH7 5
 Latches
A latch is a temporary storage device that has two
stable states (bistable). It is a basic form of
memory.
The S-R (Set-Reset) latch is the most basic type. It
can be constructed from NOR gates or NAND gates.
R S Q
Q

Q Q
S R

NOR Active-HIGH Latch NAND Active-LOW Latch

241-208 CH7 6
 S-R Latch
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW. 0 R 01
Q
Assume the latch is initially RESET Latch
(Q = 0) and the inputs are at their initially
RESET
inactive level (0). To SET the latch 10
Q
(Q = 1), a momentary HIGH signal 0 S
is applied to the S input while the R 0 R 01
remains LOW. Q
Latch
To RESET the latch (Q = 0), a initially
momentary HIGH signal is SET
01
applied to the R input while the S Q
0 S
remains LOW.

241-208 CH7 7
 S-R Latch (cont.)
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH. 1 S 01
Q
Assume the latch is initially RESET
Latch
(Q = 0) and the inputs are at their initially
inactive level (1). To SET the latch RESET
(Q = 1), a momentary LOW signal 01
1 R Q
is applied to the S input while the R
remains HIGH. 1 S 01
Q
To RESET the latch a momentary Latch
LOW is applied to the R input initially
while S is HIGH.
01 SET
Never apply an active set and 1R Q
reset at the same time (invalid).

241-208 CH7 8
 Latch with Enable
A gated latch is a variation on the basic latch.
The gated latch has an additional S
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Show the Q output with Q
relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R

EN
Q
241-208 CH7 9
 D Latch
The D latch is an variation of the S-R latch but combines
the S and R inputs into a single D input as shown:

D D Q
Q

EN EN

Q
Q

A simple rule for the D latch is:

Q follows D when the Enable is active.

241-208 CH7 10
 Truth Table of D Latch
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output and it is
latched.

Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change

241-208 CH7 11
 D Q

Example EN

Q
Determine the Q output for the
D latch, given the inputs shown.

EN

Notice that the Enable is not active during these times, so

the output is latched.

241-208 CH7 12
 Edge-Triggered Flip-Flops
Circuit type: Synchronous bistable device
Q:What is bistable ?
A: Remain in one of two stable states until it receives
a pulse
(logic 1 signal) through one of its inputs, upon which it
switches, or flips, over to the other state.

241-208 CH7 13
 Edge-Triggered Flip-Flops (cont.)
ET-FF characteristics:
1-bit storage devices
Why? 1) Since outputs can be set to store either 0 or
1, depending on the inputs
2) outputs retain their prescribed values
(bistable prop.)
FF have 2 complimentary outputs (Q, Q)
Three main FF types: R-S, D-type, J-K
Changes state either at the positive or negative
edge of the clock pulse

241-208 CH7 14
 Edge-Triggered Flip-Flops (cont.)

The active edge can be positive or negative.

D Q D Q

C C

Dynamic
Q Q
input
indicator (a)Positiveedgetriggered (b)Negativeedgetriggered

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments

1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

241-208 CH7 15
 Edge-Triggered Flip-Flops (cont.)
1. More versatile than other FFs.
J Q
2. Has 2 inputs (J and K) and 2 outputs
CLK

K Q

Positive ET-J-K
FF
symbol

241-208 CH7 16
 Edge-Triggered Flip-Flops (cont.)

241-208 CH7
 Edge-Triggered Flip-Flops (cont.)
J Q

CLK

K Q

Positive ET-J-K FF truth table

Inputs Outputs
J K CLK Q Q Comments
How comes ? 0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

241-208 CH7 18
 Edge-Triggered Flip-Flops (cont.)
Inputs Outputs
Here is one example to test your understanding.
J K CLK Q Q Comments

0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

Consider only
positive-edged of
the clock pulse

241-208 CH7 19
 Edge-Triggered Flip-Flops (cont.)
Inputs Outputs

One more example and try to figure outJ K CLK Q Q Comments

by yourself !! 0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

Se Toggle Se Latch
t t
CLK

J
K
Q

241-208 CH7 20
 Edge-Triggered Flip-Flops (cont.)
Asynchronous Preset and Clear inputs
FF outputs are independent of the clock if either Preset
Clear is asserted.
PRE

J Q

CLK

K Q

CLR

241-208 CH7 21
 Edge-Triggered Flip-Flops (cont.)

Check by yourself for this example !

Set Toggle Set Reset Toggle Latch PRE

CLK

J J Q

K Set CLK

PRE Reset
K Q
CLR

Q CLR

241-208 CH7 22
 FFs Operating Characteristics
Propagation delay time is specified for the
rising and falling outputs. It is measured between
the 50% level of the clock to the 50% level of the
output transition.
50% point on triggering edge

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q

tPLH tPHL

The typical propagation delay time for the 74AHC family

(CMOS) is 4 ns. Even faster logic is available for specialized
applications.
241-208 CH7 23
 FFs Operating Characteristics
(cont.)
Another propagation delay time specification is
the time required for an asynchronous input to
cause a change in the output. Again it is measured
from the 50% levels. The 74AHC family has specified
delay times under 5 ns.

PRE 50% point CLR 50% point

Q 50% Q 50% point

point

tPHL tPLH

241-208 CH7 24
 FFs Operating Characteristics
(cont.)
Set-up time and hold time are times required
before and after the clock transition that data
must be present to be reliably clocked into the
flip-flop. D
Setup time is the
minimum time for the CLK
data to be present
before the clock. Set-up time, ts

D
Hold time is the
minimum time for the CLK
data to remain after the
clock.
Hold time, tH

241-208 CH7 25
 FFs Operating Characteristics
(cont.)
Some other important characteristics are:-

Maximum clock frequency

Pulse widths

Power dissipation

Speed-power product

241-208 CH7 26
 FF Applications

Parallel data storage

Frequency division

Counter (will be illustrated in detail later o

241-208 CH7 27
 FF Applications (cont.)
Output
Data storage lines
D Q0
Data is stored until the next clock C

pulse. R

D Q1
PRE
C

J Q
D Q2
C
CLK Parallel data
input lines R

K Q D Q3
Clock C

CLR R
Clear

241-208 CH7 28
 FF Applications (cont.)
For frequency division, it is simple to use a
flip-flop in the toggle mode or to chain a series
of toggle flip flops to continue to divide by two.
HIGH HIGH
One flip-flop will divide fin
by 2, two flip-flops will QA QB fout
J J
divide fin by 4 (and so
on). A side benefit of fin CLK CLK
frequency division is that
the output has an exact K K

50% duty cycle. fin

Waveforms:

fout

241-208 CH7 29
 Counter
Counting in binary.

0 0 0
0 0 1
0 1 0 LSB changes on
every number.
0 1 1
1 0 0
The next bit
1 0 1
changes on every
fourth number. 1 1 0
1 1 1 The next bit
changes on every
other number.
241-208 CH8 30
 Counter (cont.)
Counter can be formed by connecting FFs
together

Counter can be categorized into two

cases, according to the ways they are
clocked !!
Asynchronous counter (ripple counter)
Each FF formed counter do not change
their states at the same time
Synchronous counter
241-208 CH8 31
 Asynchronous Counters
Three bit asynchronous counter
In an asynchronous counter, the clock is
applied only to the first stage.
Subsequent stages derive the clock
from the previous
The three-bit stage.
asynchronous counter shown is
typical. It uses J-K flip-flops in the toggle
mode.
HIGH

J0 Q0 J1 Q1 J2 Q2

CLK C C C
Q0 Q1
K0 K1 K2

Waveforms are on the

241-208 CH8 32
 Asynchronous Counters (cont.)
Notice that the Q0 output is triggered on the
leading edge of the clock signal. The
following stage is triggered from Q0. The
leading edge of Q0 is equivalent to the
trailing edge
1 of
2 Q30. The
4 resulting
5 6 7 sequence
8 is
CLK
that of an 3-bit binary up counter.
Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

241-208 CH8 33
 Asynchronous Counters (cont.)
Propagation delay
Asynchronous counters are sometimes called
ripple counters, because the stages do not all
change together. For certain applications
requiring high clock rates, this is a major
disadvantage. CLK 1 2 3 4

Notice how delays Q0

are cumulative as
Q1
each stage in a
counter is clocked Q2
later than the
previous stage.

Q0 is delayed by 1 propagation delay, Q2 by 2 delays and

241-208 CH8 Q3 by 3 delays. 34
 Asynchronous Counters (cont.)
The modulus of a counter is the number of output s
goes through before returning its self back to zero.

The maximum possible number of states (maximum

of a counter is 2n
HIGH

J0 Q0 J1 Q1 J2 Q2 Counter with 3 FFs

count from 0-7 and
CLK C C C
called modulo-8
Q0 Q1
K0 K1 K2 counter.
Counters can be designed to have a number of stat
sequences <2n. This type of sequence is called a
truncated sequence.
241-208 CH8 35
 Asynchronous Counters (cont.)
Asynchronous decade counter
This counter uses partial decoding to recycle
the count sequence to zero after the 1001
state (modulo-10 counter).

HIGH
CLR
Q0 Q1 Q2 Q3
J0 J1 J2 J3

CLK C C C C

K0 K1 K2 K3

Use the output of NAND

to clear input of the FFs
241-208 CH8 36
 Asynchronous Counters (cont.)
Asynchronous decade counter (cont.)

When Q1 and Q3 are HIGH together, the

counter is cleared by a glitch on the
CLR line.
1 2 3 4 5 6 7 8 9 10
CLK
Q0

Q1 Glitc
Glitch
h
Q2

Q3

CLR
241-208 CH8
Glitc
Glitch
37
 Asynchronous Counters (cont.)
The 74LS93A asynchronous counter
The 74LS93A has one independent toggle J-K
flip-flop driven by CLK A and three toggle J-K
flip-flops that form an asynchronous counter
driven
The by can
counter CLKbe
B.extended to form a 4-bit counter
by connecting Q0 to the CLK B input. Two inputs are
provided that
CLKBclear the count.
(1)

J J J J
(14) 0 1 2 3

CLKA C C C C

K0 K1 K2 K3

(2)
All J and K RO(1)
(3)
inputs are RO(2)
(12) (9) (8) (11)
connected
internally
241-208 CH8 Q0 Q1 Q2 Q3 38
 Synchronous Counters
All flip-flops are clocked together with a
common clock pulse.
Trade small propagation delays with more
circuitry to control states changes.
Toggle mode

241-208 CH8 39
 Synchronous Counters (cont.)

Timing diagram of 2-bit synchronous counter

241-208 CH8 40
 Synchronous Counters (cont.)
3-bit binary synchronous
counter HIGH Q 0

Q0Q1
Q0 Q1 Q2
J J J
0 1 2
C C C

K0 K1 K2

CLK

Timing diagram of 3-bit synchronous counter

241-208 CH8 41
 Synchronous Counters (cont.)
Analysis of synchronous counters (Tabular techniq
1. Put the counter in an
HIGH Q0
arbitrary state; then
determine the inputs for this Q0Q1
Q0 Q1 Q2
state. J J J
2. Use the new inputs to 0 1 2

determine the next state: Q2 C C C

and Q1 will latch and Q0 will K0 K1 K2
toggle.
CLK
3. Set up the next group of
inputs from the current
output. Outputs Logic for inputs
Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1

0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0 4. Q2 will latch again but both Q1 and Q0 will
241-208 CH8 toggle. 42
 Synchronous Counters (cont.)
Analysis of synchronous counters (Tabular techniq
Outputs Logic for inputs
Q2 Q1 Q0 J2 = Q0Q1 K2 = Q0Q1 J1 = Q0 K1 = Q0 J0 = 1 K0 = 1
0 0 0 0 0 0 0 1 1
0 0 1 0 0 1 1 1 1
0 1 0 0 0 0 0 1 1
0 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1 1
1 0 1 0 0 1 1 1 1

1 1 0 0 0 0 0 1 1
1 1 1 1 1 1 1 1 1
0 0 0
At this points all states have been
241-208 CH8
accounted for and the counter is ready to 43
 Synchronous Counters (cont.)
A 4-bit synchronous binary counter
Q1Q0
G1 Q2Q1Q 0
G2
FF0 FF1 FF2 FF3

HIGH J0 Q0 J1 Q1 J2 Q2 J3 Q3

CLK C C C C

K0 Q0 K1 Q1 K2 Q2 K3 Q3

The 4-bit binary

counter has one more
AND gate than the 3- Q0

bit counter just Q1

described. The
shaded areas show Q2
where the AND gate
outputs are HIGH Q3
causing
241-208 CH8 the next FF 44
 Synchronous Counters (cont.)
4-bit synchronous decade counter
With some additional logic, a binary counter
can be converted to a BCD synchronous
decade counter. After reaching the count
1001,
This the
gate counter
detects recycles
1001, to 0000.
and causes FF3 to
toggle on the next clock pulse. FF0 toggles
on every clock pulse. Thus, the count starts
Q
over at 0000.
3
HIGH Q 0

FF0 FF1 FF2 FF3

J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

241-208 CH8 45
 Synchronous Counters (cont.)
Waveforms for the decade counter:
1 2 3 4 5 6 7 8 9 10
CLK
Q0 0 1 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0 0 0

Q2 0 0 0 0 1 1 1 1 0 0 0

Q3 0 0 0 0 0 0 0 0 1 1 0

HIGH
FF0 FF1 FF2 FF3

J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

241-208 CH8 46
 Synchronous Counters (cont.)
A 4-bit synchronous binary counter in IC form
The 74LS163 is a 4-bit IC synchronous counter
with additional features over a basic counter. It
has parallel load, a CLR input, two chip enables,
and a ripple count output that signals when the
count has reached the terminal count.
Data inputs
D0 D1 D2 D3

(3) (4) (5) (6)

CLR (1) CTR DIV 16

(Ripple Clock Output)
(9)
LOAD
(10) (15)
goes high when count to
ENT
(7)
TC = 15 RCO state 15
ENP
(2)
CLK C

(14) (13) (12) (11)

Both enable
I/Ps Q0 Q1 Q2 Q3

241-208 CH8 Data 47

 Synchronous Counters (cont.)
CLR
LOAD
D0
D1
Data
inputs D2

D3

CLK
ENP
ENT

Q0
Q1
Data
outputs Q2
Q3

RCO
12 13 14 15 0 1 2

Count Inhibit
241-208 CH8 Clear 48
 Up/Down Synchronous Counters
Counting in either direction (also called a bi-direct

Says if ud like to design a 3-bit up/down counter

Clock pulse Up Q2 Q1 Q0 Down
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Down/ Q2 changes states
Up/ Q2
when changes statesDown/Up/
Q1&Q0=0
Q1 changes states Always toggle,
Q1 changes states
when Q1&Q0=1 when Q0=0 hence J0=K0 =1
when Q0=1
241-208 CH8 49
 Up/Down Synchronous Counters
(cont.)

UP

HIGH
FF0 FF1 FF2
Q2
J J J
Q0 Q1
0 1 2
UP/DOWN C C C
Q0 Q1 Q2
K0 K1 K2

DOWN
Q0.DOWN
CLK

Basic 3-bit up/down synchronous counter

241-208 CH8 50
 Up/Down Synchronous Counters
(cont.)
D0 D1 D2 D3 Data inputs

(15) (1) (10) (9)

The 74HC190 is a high 74HC190
(4) (12)
CTEN MAX/MIN
speed CMOS synchronous D/U
(5)
(11) CTR DIV 10
up/down decade counter LOAD (14) (13)
CLK C RCO
with parallel load
(3) (2) (6) (7)
capability. It also has a
active LOW ripple clock Q0 Q1 Q2 Q3 Data outputs

output (RCO) and a D0 D1 D2 D3 Data inputs

MAX/MIN output when the
terminal counthas
The 74HC191 is reached.
the 74HC191 (15) (1) (10) (9)
(4) (12)
CTEN
same inputs and D/U
(5)
MAX/MIN
CTR DIV 16
outputs but is a (11)
LOAD (14) (13)
C RCO
synchronous up/down CLK
(3) (2) (6) (7)
binary counter.
Q0 Q1 Q2 Q3 Data outputs
241-208 CH8 51
 Design of Synchronous Counters
General model of a sequential circuit

241-208 CH8 52
 Design of Synchronous Counters
(cont.)
Design procedure for synchronous counters
Step I: State diagram 000
100 001

101 011

111 010
110
Step II: Next state
table:
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0

241-208 CH8 53
 Design of Synchronous Counters
(cont.)
Step III: FF transition table
The J-K transition table lists all combinations of present
output (QN) and next output (QN+1) on the left. The
inputs that produce that transition are listed on the
right.
Output Flip-Flop
Transitions Inputs
QN Q N+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Each time a flip-flop is clocked, the J and K

inputs required for that transition are mapped
241-208onto
CH8 a K-map. 54
 Design of Synchronous Counters
(cont.)
Step IV: K-maps

Example of mapping procedure

241-208 CH8 55
 Design of Synchronous Counters
(cont.)
Step IV: K-maps (cont.)

K-maps for present-state J&K inputs

241-208 CH8 56
 Design of Synchronous Counters
(cont.)
Step V: Logic expressions

241-208 CH8 57
 Design of Synchronous Counters
(cont.)
Step VI: Counter implementation

FF0 FF1 FF2

Q2
J J1 J
Q0 Q1
0 2
C C C
Q0 Q1 Q2
K0 K1 K2

CLK

241-208 CH8 58
 Cascaded counters
Cascading is a method of achieving higher-
modulus counters. For synchronous IC counters,
the next counter is enabled only when the
terminal countTwo
of the previous
cascaded stage is reached.
asynchronous counter

241-208 CH8 Timing diagram 59

 Cascaded Counters (cont.)

HIGH
in
Counter 1 Counter 2
16 fout in
CTEN TC CTEN TC 256
CTR DIV 16 CTR DIV 16
CLK C Q0 Q1 Q2 Q3 C Q0 Q1 Q2 Q3
fin

Modulus-256 synchronous counter using two cascaded synchrono

241-208 CH8 60
 Counter Decoding
Decoding is the detection of a binary
number and can be done with an AND
gate. HIGH
Q2
J0 Q0 J1 Q1 J2 Q2

C C C
Q0 Q1
K0 Q0 K1 Q1 K2 Q2

CLK
1 1 1
LSB MSB

1.What number is decoded by

this gate? Decoded4
2. How to modify it in order to
Q2Q1Q0
provide
241-208 CH8active-LOW decoding? 61
 Counter Decoding (cont.)
Decoding glitches

BCD counter and decoder

241-208 CH8 62
 Counter Decoding (cont.)
Way to eliminate glitches

BCD counter and decoder with strobing

241-208 CH8 63
 Counter Applications
Digital clocks

241-208 CH8 64
 Typical divide-by-60
Counter

CLR CTRDIV10 CLR CLR CTRDIV6

RCO
HIGH CTEN TC=9 CTEN

C C
CLK Tonext
Decode6 counter

TC=59
ToENABLE
Decode59 ofnextCTR
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

units tens

241-208 CH8 65
 Hours Counter

241-208 CH8 66
 Counter Applications (cont.)
Automobile parking control

241-208 CH8 67
 Basic Shift Register Functions
A shift register is an arrangement of flip-flops with
important applications in storage and movement of data.

Data in

Data in Data out Data out Data in Data out

Serial in/shift right/serial Serial in/shift left/serial out Parallel in/serial out
out
Data in

Data in

Data out Data out

Serial in/parallel out Parallel in/parallel out Rotate right Rotate left

241-208 CH9 68
 Serial-in/Serial out Shift
Register
5-bit serial in/serial out shift register
implemented with D flip-flops.

FF0 FF1 FF2 FF3 FF4

Serial 1 1 1 1 1 1 Serial
data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data
input output

C C C C C

CLK
CLK

241-208 CH9 69
 Serial In/Parallel Out Shift
Registers
4-bit serial in/parallel out shift register
For example, assume the binary number 1011
is loaded sequentially, one bit at each clock
pulse.

FF0
FF0 FF1 FF2
FF2 FF3
FF3
Serial X
0
1 1
0 10
1 10 11
data D
D00 Q
Q00 D
D11 Q
Q11 D
D22 Q
Q22 D
D33 Q
Q33
input
C
C C
C C
C C
C

CLK
CLK

241-208 CH9 70
 74HC164A Shift Register
8-bit serial in/parallel out shift register
One of the two serial data inputs may be used as an active HIGH enable
to gate the other input.
If no enable is needed, the other serial input can be connected to Vcc.
The 74HC164A has an active LOW asynchronous clear.
Data is entered on the leading-edge of the clock.

(9)
CLR
(8)
CLK
(1)
Serial A
(2) R R R R R R R R
B
input C C C C C C C C
s
S S S S S S S S

(3) (4) (5) (6) (10) (11) (12) (13)

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

241-208 CH9 71
 Waveforms for the 74HC164A
CLR

A
B acts as an active Serial
B
HIGH enable for input
s CLK
the data on A.
Q0
As with CMOS Q 1

devices, unused Q 2

inputs should Q 3

always be Output
s Q 4

connected to a Q 5

logic level; unused Q 6

outputs should be Q
left open.
7

Clear Clear

241-208 CH9 72
 Parallel In/Serial Out Shift
Registers
Shift registers can be used to convert
parallel data to serial form.
D0 D1 D2 D3

SHIFT/LOAD

G1 G5 G2 G6 G3 G7 G4

Serial
D D D D
Q0 Q1 Q2 Q3 data
C C C C out

FF0 FF1 FF2 FF3

CLK

241-208 CH9 73
 74HC165 Shift Register
8-bit parallel in/serial out shift register
The clock (CLK) and clock inhibit (CLK INH) lines are
connected to a common OR gate, so either of these
inputs can be used as an active-LOW clock enable
with the other as the clock input.
Data is loaded asynchronously when SH/LD is LOW
and moved through the register synchronously when
SH/LD is HIGH and a rising clock pulse occurs.

D0 D1 D2 D3 D4 D5 D6 D7
(11) (12) (13) (14) (3) (4) (5) (6)
(1) (9)
SH/LD (10) SRG 8 Q7
SER
(15)
CLK INH (2) (7)
CLK C Q7

241-208 CH9 74
 74HC165 (cont.)

241-208 CH9 75
 Parallel In/Parallel Out Shift
Registers

241-208 CH9 76
 Sample Timing Diagram

241-208 CH9 77
 Bidirectional Shift Register
Bidirectional shift registers can shift the
data in either direction using a
RIGHT/LEFT input.

241-208 CH9 78
 Example

CLK
RIGHT/LEF Shift left Shift
T
Serial data in right

Q0
Q1
Q2
Q3

How will the pattern change if the

RIGHT/LEFT control signal is inverted?

241-208 CH9 79
 Example (cont.)

CLK
RIGHT/LEF Shift
Shiftleft ShiftShift left
T
Serial data in right right

Q0
Q1
Q2
Q3

241-208 CH9 80
 Universal Shift Register
A universal shift register has both serial and parallel
input and output capability. The 74HC194 is an
example of a 4-bit bidirectional universal shift
register.
D0 D1 D2 D3

(3) (4) (5) (6)

(1)
CLR SRG 4
(9)
S0
(10)
S1
(2)
SR SER
(7)
SL SER
(11)
CLK C
(15) (14) (13) (12)

Q0 Q1 Q2 Q3
241-208 CH9 81
 Sample Waveforms
CLK

Mode S0
control
inputs S1

CLR

Serial SR SER
data
inputs SL SER

D0
Parallel D1
data
inputs D2
D3

Q0

Q1
Parallel
outputs
Q2

Q3
Shift right Shift left Inhibit
Clear Load Clear

241-208 CH9 82
 Shift Register Counters
Shift registers can form useful counters by
recirculating a pattern of 0s and 1s. Two
important shift register counters are the Johnson
counter and the ring counter.
The Johnson counter can be made with a series of
either D flip-flops or J-K flip-flops.
FF0 FF1 FF2 FF3 FF0 FF1 FF2 FF3
Q3
D0 Q0 D1 Q1 D2 Q2 D3 Q3 J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3
Q3 Q3

CLK CLK

241-208 CH9 83
 Johnson counter
The Johnson counter is useful when you need a sequence
that changes by only one bit at a time but it has a
limited number of states (2n, where n = number of
stages).
The first five counts for a 4-bit Johnson counter that is
initially cleared are: CLK Q0 Q1
Q2 Q3 0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
What are the remaining 3
states?
241-208 CH9 84
 Ring Counter
The ring counter can also be implemented
with either D flip-flops or J-K flip-flops.
4-bit ring counters are constructed from a
series of D flip-flops and J-K flip-flops.
Notice the feedback.
FF0 FF1 FF2 FF3
FF0 FF1 FF2 FF3
Q3
Q3 J0 Q0 J 1 Q1 J 2 Q2 J 3 Q3
D0 Q0 D1 Q1 D2 Q2 D3 Q3
C C C C
C C C C
Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK
CLK

Describe the disadvantage and advantage of

241-208 CH9 the ring counter? 85
 Ring Counter
A common pattern for a ring counter is to load it
with a single 1 or a single 0. The waveforms shown
here are for an 8-bit ring counter with a single 1.
CLK 1 2 3 4 5 6 7 8 9 10

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

241-208 CH9 86
 Shift Register Applications
Examples: Time Delay, Parallel/Serial Data Converter, and
Keyboard Encoder
An 8-bit serial in/serial out shift register has a 40 MHz
clock. What is the total delay through the register?

A SRG 8 Q7
Data in Data out
B
Q7
The delay for each CLK
40 MHz
C

clock is 1/40 MHz = 25

25 ns
ns
The total delay is CLK
8 x 25 ns = 200
Data in
ns
Data out
td = 200 ns

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 Parallel/Serial Data Converter

Start
D7 D6 D5 D4 D3 D2 D1 D0 Stop Bits (1)
Bit (0)
t

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 Parallel/Serial Data Converter
(cont.)

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 UART
A UART (Universal Data bus
Asynchronous Receiver
Transmitter) is a serial-to-
Buffers
parallel converter and a
parallel to serial converter.
UARTs are commonly used Transmitter Receiver
in small systems where one data register data register

device must communicate

with another. Parallel data Transmitter Receiver
CLK CLK
is converted to shift register shift register

asynchronous serial form

and transmitted. Serial data out Serial data in

241-208 CH9 90
 Keyboard Encoder
The keyboard encoder is an example
of where a ring counter is used in a
small system to encode a key press.
Two 74HC195 shift registers are

connected as an 8-bit ring counter

preloaded with a single 0.
As the 0 circulate in the ring counter,

it scans the keyboard looking for

any row that has a key closure.
When one is found, a corresponding

column line is connected to that row

241-208 CH9 91
 Power on LOAD
SH/LD +VCC
Ring counter

D0 D1 D2 D3 D4 D5 D6 D7
J J
K SRG 4 K SRG 4
CLK 74HC195 74HC195
(5 kHz) C C +V
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Clock inhibit

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ROW encoder COLUMN encoder
74HC147 74HC147
1 2 4 1 2 4

Switch closure
Q Q D0 D1 D2 D3 D4 D5
C
Key code register
74HC174
C C
Q0 Q1 Q2 Q3 Q4 Q5

Q
One-shots To ROM
 Conclusion
ET FFs is a synchronous bistable device, whose
state depends on the input only at the triggering
transition of a clock pulse
JK-FFs is mostly used since we can design other FF
types (D,RS) with JK-FF.
Applications of FFs are frequency division, counter,
and storage device.

241-208 CH7 93