Implement Write-invalidate protocol to

demonstrate the memory coherency

By:
-Puneeth
-Sonal
-Nagarjuna.E
-Sangeeta Patil
What is Cache-coherence
Cache coherence is the discipline that ensures that
changes in the values of shared operands are
propagated throughout the system in a timely fashion.
In a shared memory multiprocessor with a
separate cache memory for each processor , it is
possible to have many copies of any one
instruction operand (one copy in the main memory and
one in each cache memory).
When one copy of an operand is changed, the other
copies of the operand must be changed also.Cache-
coherence takes care.
Snooping Protocol Types

Write-Invalidate :

When a processor writes on a shared cache block, all the shared copies
in the other caches areinvalidatedthrough bus snooping. This method
ensures that only a copy of a data can be exclusively read and written
by a processor. All the other copies in other caches are invalidated.

Write-update :
When a processor writes on a shared cache block, all the shared
copies of the other caches are updated through bus snooping. This
method broadcasts a write data to all caches throughout a bus. It
incurs larger bus traffic than write-invalidate protocol. That is why
this method is uncommon. Dragon and firefly protocols belong to
this category.
Write-Invalidate Write-Through Protocol

State Description
Valid [VALID] - The copy is consistent with global memory.
Invalid [INV] - The copy is inconsistent.

Events
Read-Hit - Use the local copy from the cache.
Read-Miss - Fetch a copy from global memory. Set the state of this copy
to Valid.
Write-Hit - Perform the write locally. Broadcast an Invalid command to all
caches. Update the global memory.
Write-Miss - Get a copy from global memory. Broadcast an invalid
command to all caches. Update the global memory. Update the local
copy and set its state to Valid.
 Write-through Invalidate Protocol
In this simple protocol the memory is always consistent
with the most recently updated cache copy.
Multiple processors can read block copies from main
memory safely until one processor updates its copy.
At this time, all cache copies are invalidated and the
memory is updated to remain consistent.
Write-through Invalidate Protocol
 Write-Back Invalidate Protocol
In this protocol a valid block can be owned
by memory and shared in multiple caches
that can contain only the shared copies of
the block.
Multiple processors can safely read these
blocks from their caches until one processor
updates its copy.
At this time, the writer becomes the only
owner of the valid block and all other copies
are invalidated.
Write-Back Invalidate Protocol
Advantages and
Disadvantages
Advantage: good performance for
Many updates between reads
Per node locality of reference
Disadvantage
Invalidations sent to all nodes that have
copies
Inefficient if many nodes access same
object
Examples: most DSM systems: IVY, Clouds,
Dash,Memnet, Mermaid, and Mirage
Thank you