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  • 1 Illustration of Technology

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    1. The document discusses the scaling down of technology over time, showing decreasing feature sizes from the 1980s to early 2000s. 2. It outlines the roadmap for technology, including decreasing feature sizes and increasing device density. Feature sizes shrink from 2 microns in the 1980s to 0.02 microns by 2000. 3. Key topics covered include major players in the semiconductor industry in France, the scaling of the MOS transistor and challenges associated with it, and how scaling impacts inverters and integrated circuit performance over time.

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    illustration of technologi

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    1. The document discusses the scaling down of technology over time, showing decreasing feature sizes from the 1980s to early 2000s. 2. It outlines the roadmap for technology, including decreasing feature sizes and increasing device density. Feature sizes shrink from 2 microns in the 1980s to 0.02 microns by 2000. 3. Key topics covered include major players in the semiconductor industry in France, the scaling of the MOS transistor and challenges associated with it, and how scaling impacts inverters and integrated circuit performance over time.

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    © All Rights Reserved
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    Signaler comme contenu inapproprié
    14 vues20 pages

    1 Illustration of Technology

    Transféré par

    sry
    1. The document discusses the scaling down of technology over time, showing decreasing feature sizes from the 1980s to early 2000s. 2. It outlines the roadmap for technology, including decreasing feature sizes and increasing device density. Feature sizes shrink from 2 microns in the 1980s to 0.02 microns by 2000. 3. Key topics covered include major players in the semiconductor industry in France, the scaling of the MOS transistor and challenges associated with it, and how scaling impacts inverters and integrated circuit performance over time.

    Droits d'auteur :

    © All Rights Reserved
    Téléchargez comme PPT, PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 20

    1.

    Illustration of the
    Technology Scale down
    Etienne Sicard

    etienne.sicard@insa-tlse.fr
    http://intrage.insa-tlse.fr/~etienne
    Summary

    1. Whos who
    2. Road map
    3. The MOS device
    4. The inverter
    5. Conclusion

    03/12/17 E. Sicard - Technolog 2


    1. Whos who in France

    Philips
    Philips Ibm
    ST rennes

    Atmel Atmel
    ST Tours ST Grenoble

    Texas, VLSI
    Motorola ST, Atmel Cadence

    03/12/17 E. Sicard - Technolog 3


    2. Roadmap
    Bits
    10 DRAM 4G
    1G
    GIGA
    256M
    1 GIGA
    64M
    100 MEG
    16M
    4M
    10 MEG
    1M
    1 MEG 256K

    100K
    Year
    83 86 89 92 95 98 01 04
    Anne
    03/12/17 E. Sicard - Technolog 4
    2. Roadmap
    Technology
    (m) 2.0
    80286 Production
    80386
    1.0 486
    pentium
    0.3 pentium II
    0.2 Pentium IV
    Research
    0.1

    0.05
    0.03

    83 86 89 92 95 98 01 04
    Year
    03/12/17 E. Sicard - Technolog 5
    2. Roadmap
    Leti
    1 MOS
    0.02m
    Dec. 2000

    IBM
    106 MOS
    0.015m
    Nov. 2001
    03/12/17 E. Sicard - Technolog 6
    2. Roadmap
    0.5 m 0.18 m 0.12m

    Devices

    1995
    2000 2002

    Interconnects 3 layers 7 layers 8 layers

    Frequency

    120MHz 500MHz 1500 MHz


    03/12/17 E. Sicard - Technolog 7
    2. Roadmap
    Technology Year Metal Supply (V) Oxide(A) Vt (V) ST technology
    0.7m 1988 2 5.0 200 0.7 Hcmos4
    0.5m 1992 3 3.3 120 0.6 Hcmos5
    0.35m 1994 5 3.3 75 0.5 Hcmos6
    0.25m 1996 6 2.5 65 0.45 Hcmos7
    0.18m 1999 7 1.9 50 0.40 Hcmos8
    0.12m 2001 8 1.5 40 0.30 Hcmos9
    0.10m 2003 8-9 1.0 35 0.25 Hcmos10

    03/12/17 E. Sicard - Technolog 8


    2. Roadmap
    Supply (V)
    Chip I/Os
    5.0
    I/O trend
    3.3 Chip Core

    2.5
    1.5
    Core trend

    Technology (m)
    0.5 0.35 0.18 0.10 0.07
    03/12/17 E. Sicard - Technolog 9
    2. Roadmap
    Radiation
    Typical wire load (fF)

    100

    75

    50

    25 Charge
    Charges (C.V) Technology
    0.5 0.35 0.18 0.10 0.07 (m)
    Soft error due to radiation becomes probable
    03/12/17 E. Sicard - Technolog 10
    3. The MOS device

    1 3 2

    I V
    3
    demo
    1 Little quiz 2
    V
    03/12/17 E. Sicard - Technolog 11
    3. The MOS device

    0 1

    0 1

    Ron close from 1000 demo

    03/12/17 E. Sicard - Technolog 12


    3. The MOS device

    1 1
    1
    0 Good 0 Bad 1

    0 0
    1
    0 Good 1
    Bad 0

    Technology scale down keeps those drawbacks


    03/12/17 E. Sicard - Technolog 13
    3. The MOS device
    R off Static
    Current (A)
    100 M 1

    10 M 0.1 1 MT block

    1 M 0.01
    100K Low leakage MOS 0.001

    Technology (m)
    0.5 0.35 0.18 0.10 0.07
    03/12/17 E. Sicard - Technolog 14
    3. The MOS device
    Low power
    High Speed High Voltage

    3.3V

    03/12/17 E. Sicard - Technolog 15


    4. The inverter
    In

    Out

    Time
    In0.25m typical delay 50ps
    Depends on conditions (10,90%)
    demo
    Depends on charge (capacitance)
    03/12/17 E. Sicard - Technolog 16
    4. The inverter
    Idd (mA)

    In, Out
    (V)
    Time

    Current peaks 0.2mA


    03/12/17 E. Sicard - Technolog 17
    4. The inverter

    Delay (ns)

    Interconnection (m)

    03/12/17 E. Sicard - Technolog 18


    4. The inverter
    Ring oscillator
    0.7m

    0.25m

    Frequencies x 5 although VDD divided by 2


    03/12/17 E. Sicard - Technolog 19
    Conclusion

    Illustration of technology scale down


    Continuous gain in frequency
    Power supply reduction
    The MOS keeps the same, but many versions
    Increased interconnects improve density
    In 2002, ST will produce the 0.12m technology

    03/12/17 E. Sicard - Technolog 20

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