IEP on Synthesis of Digital Design 2007 Adder Circuits

Adder Circuits
IEP on Synthesis of Digital Design 2007 Adder Circuits

Acknowledgement
Slides taken from http://
bwrc.eecs.berkeley.edu/IcBook/index.htm
which is the web-site of Digital Integrated Circuit A Design
Perspective by Rabaey, Chandrakasan, Nicolic
IEP on Synthesis of Digital Design 2007 Adder Circuits

Outline
Background / Basics of Adders
Ripple Carry Adder
IEP on Synthesis of Digital Design 2007 Adder Circuits

A Generic Digital Processor

MEM ORY
INPUT-OUTPUT

CONTROL

DATAPATH
IEP on Synthesis of Digital Design 2007 Adder Circuits

Building Blocks for Digital Architectures

Arithmetic unit
- Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.)

Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
IEP on Synthesis of Digital Design 2007 Adder Circuits

Bit-Sliced Design
Control

Bit 3

Data-Out
Multiplexer
Bit 2
Data-In

Register

Adder

Shifter
Bit 1
Bit 0

Tile identical processing elements

IEP on Synthesis of Digital Design 2007 Adder Circuits

Bit-Sliced Datapath
From register files / Cache / Bypass

Multiplexers
Shifter
Adder stage 1
Wiring
Loopback Bus
Loopback Bus

Loopback Bus
Adder stage 2

Wiring
Bit slice 63

Bit slice 2
Bit slice 1
Bit slice 0
Adder stage 3

Sum Select

To register files / Cache

IEP on Synthesis of Digital Design 2007 Adder Circuits

Itanium Integer Datapath

Fetzer, Orton, ISSCC02

IEP on Synthesis of Digital Design 2007 Adder Circuits

Full-Adder
A B

Cin Full Cout

adder

Sum
IEP on Synthesis of Digital Design 2007 Adder Circuits

The Binary Adder

A B

Cin Full Cout

adder

Sum

S = A B Ci

= ABC i + ABC i + ABC i + ABCi

C o = AB + BC i + ACi
IEP on Synthesis of Digital Design 2007 Adder Circuits

Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB
Propagate (P) = A B
Delete = A B

Can also derive expressions for S and C o based on D and P

Note that we will be sometimes using an alternate definition for
Propagate (P) = A B
IEP on Synthesis of Digital Design 2007 Adder Circuits

The Ripple-Carry Adder

A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 Co,1 Co,2

FA FA FA FA
( Ci,1)

S0 S1 S2 S3

Worst case delay linear with the number of bits

td = O(N)

tadder = (N-1)tcarry + tsum

Goal: Make the fastest possible carry path circuit

IEP on Synthesis of Digital Design 2007 Adder Circuits

Complimentary Static CMOS Full Adder

VDD

VDD
Ci A B

A B
A

B
Ci B
VDD
A
X
Ci

Ci A
Ci

A B B VDD
A B Ci A

Co B

28 Transistors
IEP on Synthesis of Digital Design 2007 Adder Circuits

Inversion Property
A B A B

Ci FA Co Ci FA Co

S S

S A B C i = S A B C i

C o A B C i = Co A B Ci
IEP on Synthesis of Digital Design 2007 Adder Circuits

Minimize Critical Path by Reducing Inverting Stages

Even cell Odd cell

A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 Co,1 C Co,3

FA FA FA FA

S0 S1 S2 S3

Exploit Inversion Property

IEP on Synthesis of Digital Design 2007 Adder Circuits

A Better Structure: The Mirror Adder

VDD

VDD VDD A

A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A

24 transistors
IEP on Synthesis of Digital Design 2007 Adder Circuits

Mirror Adder
Stick Diagram
VDD

A B Ci B A Ci Co Ci A B

Co

GND
IEP on Synthesis of Digital Design 2007 Adder Circuits

The Mirror Adder

The NMOS and PMOS chains are completely symmetrical.
A maximum of two series transistors can be observed in the carry-
generation circuitry.
When laying out the cell, the most critical issue is the minimization
of the capacitance at node Co. The reduction of the diffusion
capacitances is particularly important.
The capacitance at node Co is composed of four diffusion
capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell .
The transistors connected to Ci are placed closest to the output.
Only the transistors in the carry stage have to be optimized for
optimal speed. All transistors in the sum stage can be minimal
size.
IEP on Synthesis of Digital Design 2007 Adder Circuits

Transmission Gate Full Adder

P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci

A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P
IEP on Synthesis of Digital Design 2007 Adder Circuits

Manchester Carry Chain

VDD
Pi
VDD
Pi
Ci Co
Gi
Co Gi
Ci

Di
Pi
IEP on Synthesis of Digital Design 2007 Adder Circuits

Manchester Carry Chain

VDD

P0 P1 P2 P3
C3

Ci,0
G0 G1 G2 G3

C0 C1 C2 C3
IEP on Synthesis of Digital Design 2007 Adder Circuits

Manchester Carry Chain

Stick Diagram
Propagate/Generate Row

VDD
Pi Gi Pi + 1 Gi + 1

Ci - 1 Ci Ci + 1

GND

Inverter/Sum Row
IEP on Synthesis of Digital Design 2007 Adder Circuits

Carry-Bypass Adder
P0 G1 P0 G1 P2 G2 P3 G3 Also called
Carry-Skip
Ci,0 C o,0 C o,1 Co,2 Co,3
FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA

Multiplexer
Co,3

Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C 0, else kill or generate.
IEP on Synthesis of Digital Design 2007 Adder Circuits

Carry-Bypass Adder (cont.)

Bit 03 Bit 47 Bit 811 Bit 1215
Setup tsetup Setup tbypass Setup Setup

Carry Carry Carry Carry

propagation propagation propagation propagation

Sum Sum Sum tsum Sum

M bits

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

IEP on Synthesis of Digital Design 2007 Adder Circuits

Carry Ripple versus Carry Bypass

tp
ripple adder

bypass adder

4..8
N
IEP on Synthesis of Digital Design 2007 Adder Circuits

Carry-Select Adder
Setup

P,G

"0" "0" Carry Propagation

"1" "1" Carry Propagation

Co,k-1 Multiplexer Co,k+3

Carry Vector

Sum Generation
IEP on Synthesis of Digital Design 2007 Adder Circuits

Carry Select Adder: Critical Path

Bit 03 Bit 47 Bit 811 Bit 1215
Setup Setup Setup Setup

0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry

Multiplexer Multiplexer Multiplexer Multiplexer

Ci,0 Co,3 Co,7 Co,11 Co,15

Sum Generation Sum Generation Sum Generation Sum Generation

S03 S47 S811 S
IEP on Synthesis of Digital Design 2007 Adder Circuits

Linear Carry Select

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15

Setup Setup Setup Setup

(1)

"0" Carry "0" Carry "0" Carry "0" Carry

"0" "0" "0" "0"
(1)

"1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(5) (5) (5) (5) (5)
(6) (7) (8)
Multiplexer Multiplexer Multiplexer Multiplexer
Ci,0
(9)

Sum Generation Sum Generation Sum Generation Sum Generation

S0-3 S 4-7 S8-11 S 1 2-15 (10)

IEP on Synthesis of Digital Design 2007 Adder Circuits

Square Root Carry Select

Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19

Setup Setup Setup Setup

(1)

"0" Carry "0" Carry "0" Carry "0" Carry

"0" "0" "0" "0"
(1)

"1" Carry "1" Carry "1" Carry "1" Carry

"1" "1" "1" "1"
(3) (3) (4) (5) (6) (7)
(4) (5) (6) (7)
Multiplexer Multiplexer Multiplexer Multiplexer Mux
Ci,0
(8)
Sum Generation Sum Generation Sum Generation Sum Generation Sum

S0-1 S2-4 S5-8 S9-13 S14-19 (9)

IEP on Synthesis of Digital Design 2007 Adder Circuits

Adder Delays - Comparison

50

40 Ripple adder
tp (in unit delays)

30

Linear select
20

10
Square root select

0
0 20 40 60
N
IEP on Synthesis of Digital Design 2007 Adder Circuits

LookAhead - Basic Idea

A A1, B1 AN-1, BN-1

Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1

S0 S1 SN-1

C o k = f A k B k Co k 1 = Gk + P k Co k 1
IEP on Synthesis of Digital Design 2007 Adder Circuits

Look-Ahead: Topology
Expanding Lookahead equations: VDD

C o k = Gk + Pk Gk 1 + Pk 1 Co k 2
G2

G1
All the way:
G0
C o k = Gk + Pk Gk 1 + P k 1 + P1 G0 + P0 Ci 0
Ci,0
Co,3

P0

P1

P2

P3
IEP on Synthesis of Digital Design 2007 Adder Circuits

Logarithmic Look-Ahead Adder

A0 F

A1 A2 A3 A4 A5 A6 A7

A0
tp N
A1

A2
A3
F
A4
A5

A6 tp log2(N)
A7
IEP on Synthesis of Digital Design 2007 Adder Circuits

Carry Lookahead Trees

Co 0 = G 0 + P 0 C i 0
C o 1 = G1 + P1 G0 + P 1 P0 Ci 0
C o 2 = G2 + P2 G1 + P2 P1 G0 + P 2 P1 P0 C i 0
= G2 + P2 G1 + P2 P1 G0 + P0 Ci 0 = G 2:1 + P2:1 C o 0

Can continue building the tree hierarchically.

 (A0, B0) S0

(A1, B1) S1

(A2, B2) S2

(A3, B3) S3
IEP on Synthesis of Digital Design 2007

(A4, B4) S4
Tree Adders

(A5, B5) S5

(A6, B6) S6

(A7, B7) S7

(A8, B8) S8

16-bit radix-2 Kogge-Stone tree

(A9, B9) S9

(A10, B10) S10

(A11, B11) S11

(A12, B12) S12

(A13, B13) S13

(A14, B14) S14

(A15, B15) S15

Adder Circuits
 (a 0, b 0) S0

(a 1, b 1) S1

(a 2, b 2) S2

(a 3, b 3) S3
IEP on Synthesis of Digital Design 2007

(a 4, b 4) S4
Tree Adders

(a 5, b 5) S5

(a 6, b 6) S6

(a 7, b 7) S7

(a 8, b 8) S8

16-bit radix-4 Kogge-Stone Tree

(a 9, b 9) S9

(a 10, b 10) S 10

(a 11, b 11) S 11

(a 12, b 12) S 12

(a 13, b 13) S 13

(a 14, b 14) S 14

(a 15, b 15) S 15
Adder Circuits
 (a 0, b 0) S0

(a 1, b 1) S1

(a 2, b 2) S2

(a 3, b 3) S3
IEP on Synthesis of Digital Design 2007

(a 4, b 4) S4

(a 5, b 5) S5
Sparse Trees

(a 6, b 6) S6

(a 7, b 7) S7

(a 8, b 8) S8

(a 9, b 9) S9

(a 10, b 10) S 10

(a 11, b 11) S 11

(a 12, b 12) S 12
16-bit radix-2 sparse tree with sparseness of 2

(a 13, b 13) S 13

(a 14, b 14) S 14

(a 15, b 15) S 15
Adder Circuits
 (A0, B0) S0

(A1, B1) S1

(A2, B2) S2
IEP on Synthesis of Digital Design 2007

(A3, B3) S3

Brent-Kung Tree
(A4, B4) S4
Tree Adders

(A5, B5) S5

(A6, B6) S6

(A7, B7) S7

(A8, B8) S8

(A9, B9) S9

(A10, B10) S10

(A11, B11) S11

(A12, B12) S12

(A13, B13) S13

(A14, B14) S14

(A15, B15) S15

Adder Circuits
IEP on Synthesis of Digital Design 2007 Adder Circuits

Example: Domino Adder

VDD

VDD
Clk
Gi = aibi

Clk
Pi= ai + bi ai

ai bi
bi

Clk
Clk

Propagate Generate
IEP on Synthesis of Digital Design 2007 Adder Circuits

Example: Domino Adder

VDD VDD

Clkk
Clkk
Pi:i-2k+1 Gi:i-2k+1

Pi:i-k+1 Pi:i-k+1
Gi:i-k+1

Pi-k:i-2k+1 Gi-k:i-2k+1

Propagate Generate
IEP on Synthesis of Digital Design 2007 Adder Circuits

Example: Domino Sum VDD VDD Keeper

Clk Clkd

Sum

Gi:0

Clk Si0

Clkd

Clk

Gi:0

Si1

Clk