Lecture 3

Department of Electrical &

3/19/17 1
Electronics Engineering
 Comparison between Semicustom and Full custom ICs

Semicustom Full custom

Size , speed, power Fastest

compromise
User defined logic No predefined logic
cells cells
NRE low NRE high

Time to market less Time to market high

Less opportunity for More opportunity for

performance performance
improvement improvement
 Comparison between ASIC &
Programmable ASIC

ASIC Programmab
le ASIC
NRE High Low

Risk High Low

Design time Long Quick

 Design Methodology
Top Down Approach Bottom up Approach

Designer partitions the system Designer partitions the system

based on objective criteria based on sub module availability
-speed, power, area etc.

Design not by what is available May not meet objective criteria

May produce non standard modules

May be more economical
May increase cost
Design Reuse possible

Department of Electrical &

3/19/17
Electronics Engineering
 Design Hierarchy

SystemUnits PCBsICsgatestransistors

Department of Electrical &

3/19/17
Electronics Engineering
 Design Domains

Behavioral
Structural
Physical/Geometrical

Department of Electrical &

3/19/17
Electronics Engineering
Behavioral Structural

What the system does? What are the components?

How the system respond to Information on how the components are
set of i/ps interconnected to perform certain function
Schematic, Netlist,

Physical

How the design is made

Placement & routing or manufacturing
information

Department of Electrical &

3/19/17
Electronics Engineering
 Domains and Levels of
Gajskis Y chart Modeling
Behavioral/Functional
Algorithm
Structural
Register-Transfer
Processor-
Language
Memory
Boolean Equation
Register-Transfer
Differential Equation
Gate Polygons

Transistor Sticks

Standard Cells

Floor Plan
Geometric Y-chart due
to Gajski &
1998, Peter J.
Ashenden
VHDL Quick Start Kahn
 Behavioral Structural Geometrical
Algorithm:- Processor:- Chip floor plan:-
Set of operations to be Architecture of Mapping into chip
performed processor surface
depends on
target chip
behavior

FSM/Register Transfer Register/ALUs:- Standard cells/Module

language:- Structural placement:-
How data will be moved implementation Modules placed on to
and stored chip surface using CAD
tools Routing
optimization

Boolean equation:- Leaf Sticks /Cell placement:-

How individual signals cells/Gates:- Placed &interconnected
are manipulated Structural
description

Differential equation:- Transistor :- Polygons:-

Department of Electrical & Electronics Engineering 3/19/17
Boolean description Transistor level Mask generation