CHAPTER 8

Integrated-Circuit Logic Families

Aguilar, Kim Janico

Alacapa, Maria Angelica P.
Calangian, Adriane Roy F.
Coballes, Joshua Renz A.
De Guzman, Romel A.
Teodoro, Melbert Neil G.
8.1 Digital IC Terminology
8.2 The TTL Logic Family
Most TTL circuits have a similar structure
NAND and AND gates use multiple-emitter
transistor or multiple diode junction inputs.
NOR and OR gates use separate input transistors.
The input will be the cathode of a P-N junction
A HIGH input will turn off the junction.
Only a leakage current is generated.
A LOW input turns on the junction.
Relatively large current is generated.
Most TTL circuits have some type of totem-pole
output configuration.
 The basic TTL logic circuit is the
NAND gate.

Diode equivalent
for Q1 .

Basic TTL
NAND gate.
TTL NAND gate LOW output
A TTL output acts as a current sink in the
LOW state because it receives current from
the input of the gate that it is driving.

Transistor Q4 of the driving

gate is on and essentially
shorts point X to ground.

LOW voltage at X forward-

biases the emitterbase
junction of Q1 & current
flows back through Q4.
TTL NAND gate HIGH output
A TTL output acts as a current source in the
HIGH statea small reverse-bias leakage
current.

Transistor Q3 is supplying the

input current (IIH) required
by Q1 of the load gate.

Q3 is often called the current-

sourcing or pull-up transistor.

In more modern TTL series,

the pull-up circuit is made
up of two transistors.
Internal circuit for a TTL
NOR gate.
The NOR circuit does not use
a multiple-emitter transistor.

Each input is applied to

the emitter of a separate
transistor.

The NOR circuit uses

the same totem-pole
arrangement as the NAND
circuit on the output side
8.3 TTL Data Sheets
Transistor-transistor Logic (TTL) has been
used for over 50 years and known as the
standard IC. The Texas Instruments
Corporation was the company that
manufactured the first line of TTL ICs. The
common and widely used IC family is the
series of 54/74 but it both are usually called
74. Their difference is the temperature and
power supply voltage capacity.
 Temperature Range Supply Voltage

54 4.5 to 5.5 V -55 to +125C

74 4.5 to 5.5 V 0 to 70C

When it comes to IC number, it is all the same

for the manufacturers except for the prefix
attached to the IC number.
Manufacturer prefix Sample IC

Texas Instruments Corp. SN SN7432

National Semiconductor DM DM7432

Signetics S S7432
Here are the common IC
numbers we use:
IC number Logic gate

00 Quad 2 Input NAND gate

02 Quad 2 Input +NOR gate

04 Hex Inverter

08 Quad 2 Input +AND gate

32 Quad 2 Input +OR gate

86 Quad 2 Input XOR gate

These are the various series in TTL
logic family:
TTL Series Prefix Sample IC

Standard TTL 74 7404 (hex INVERTER)

Schottky TTL 74S 74S04 (hex INVERTER)

Low-power Schottky TTL 74LS 74LS04 (hex INVERTER)

Advanced Schottky TTL 74AS 74AS04 (hex INVERTER)

Advanced low-power 74ALS 74ALS04 (hex INVERTER)

Schottky TTL
Datasheet of SN54ALS00A/
SN74ALS00A
Maximum Voltage Ratings

The voltages applied to any input of this

series IC must never exceed +0.7V, voltage
greater than +0.7V applied to an input
emitter can damage the IC and its function.
Power Dissipation
Propagation Delays
8.4 TTL SERIES
CHARACTERISTICS

TTL logic family grows into its sub-families

or the so called series. This series offers
various gates and flip flops used in small
scale integration (SSI) line.
Standard TTL, 74 Series

The standard TTL series are still available,

but it is no longer recommendable to
choose for new designs because there are
devices that are now available which
perform much better at a lower cost.
Schottky TTL, 74S Series
Introduced in 1969, the 7400 series uses
Schottky diode and operates using
saturated switching, when it is conducting,
it will be in saturated condition. Due to this
condition, it causes a storage-time delay, it
is when the transistors switches from ON to
OFF, and it limits the circuits switching
speed. These gates operate quickly in
about 3ns and higher power dissipation of
19mW.
Low-Power Schottky TTL, 74LS Series
(LS-TTL)

This series use higher resistance values

low-power TTL and Schottky diodes to have
a good combination of speed (9ns) and
lower power consumption (2mW). Used as
glue logic in microcomputers.
Advanced Schottky TTL, 74AS Series
(AS-TTL)

One of the two important innovations in the

TTL logic family is the 74AS series. The
74AS series provides a noticeable
improvement in speed versus the 74S
series at a much lower power requirement.
It is the fastest TTL series, and its power
dissipation is significantly lower than that
of the 74S series.
Advanced Low-Power Schottky TTL,
74ALS Series

74ALS series is an improved version of the

74LS series in both speed of 4ns. Among all
the TTL series, the 74ALS series has the
lowest gate power dissipation of 1.2 mW.
74FFast TTL
This series uses a new integrated-circuit
fabrication technique to reduce interdevice
capacitances to achieve reduced
propagation delays. Usually, a NAND gate
has an average propagation delay of 3 ns
and a power consumption of 6 mW. ICs in
this series are designated with the letter F
in their part number. Example, the 74F04 is
a hex-inverter chip.
Typical TTL series
characteristics
8.5 TTL LOADING AND
FAN-OUT

Fan-out refers to the maximum number of

inputs that the output of a single logic gate
can drive or feed.
Determining the Fan-Out
8.6 OTHER TTL
CHARACTERISTICS
Unconnected Inputs
Unconnected inputs to any logic signal or
ground is considered floating if all of the
inputs are in high state.
Unused Inputs
One of the characteristics of TTL is having an
unused inputs which should be corrected to
avoid improper output. Figure below shows
some ways on how to handle this kind of
occurrence.
Figure (a) is one of the example having the
said characteristic. Unused input may act as
an antenna which can receive unwanted signal
and can cause the gate to produce an
undesirable output. For a better method,
unused input should be connected to a V cc or
ground to have an input of 1 or 0; or attached
to another input as shown in Figure (b) and (c).
Tied-Together Inputs

For the connected inputs together, they

may share current from the common input.
Current from here will be the sum of the
load current of each input.
Biasing TTL Inputs Low
To bias an input to low, it is needed to
consider the value of the resistor
connected from the ground to its input. It
should not exceed to its maximum to
provide an acceptable level of output.
Formula and figure are shown below.
Current Transients
This characteristic of TTL occurs when
theres spike cause by the totem-pole
output source. An example of it is shown in
figure below. Because of the switching
transition of two transistors, this may likely
to happen.
8.7 MOS TECHNOLOGY

MOS, also known as metal-oxide-

semiconductor technology, is a structure of
metal electrode over an oxide insulator
over a semiconductor substrate.
The MOSFET
This is the field effect transistors of MOS
technology which means that theres an
effect on the resistance of substrate caused
by the electric field on the metal electrode
of the oxide insulator.
MOSFETs have two types, generally the
depletion and enhancement type.
Schematic diagram of enhancement
MOSFETs are shown below.
Basic MOSFET Switch
Figure below shows the operation of the N
channel MOSFET. In this channel, drain is
always on positive biased to the source as
shown in figure(a). VGS is used for
controlling the resistance between the
source and drain.
When VGS=0 V, the device is in the off
state or an open circuit. As it increases, it
will reach the VT (threshold voltage) which
is the starting point of the channel to be in
on state, as shown in figure (c).
On the other hand, P channel MOSFETs
have the same operation as N channel
MOSFET but it only uses an opposite
polarity for its voltage. Table below shows
the summary of each function.
8.8 DIGITAL MOSFET
CIRCUITS
PMOS
It uses a P-channel enhancement MOSFETs.
NMOS
It uses a N-channel enhancement MOSFETs.
CMOS
It uses both P- and N-channel devices.
8.9 COMPLEMENTARY
MOS LOGIC
CMOS INVERTER
When VIN = VDD, N-channel will be in
positive biased resulting to a on state.
While P-channel (Q1) will be in off state.
Thus, this input voltage will yield to a VOUT
= 0V.
If VIN = 0V, the operation will be in
opposite because of Q1 has now its gate at
negative potential. This will result to a VOUT
= +VDD. Table above shows the summary of
it operation.
CMOS NAND Gate
This gate is formed by adding another P-
channel and N-channel in the CMOS
inverter as shown in the figure below.
 When at least one of the PMOS is on
and NMOS is off, this will yield to a high
state. When the inputs are in high state,
PMOS will be in on state while NMOS will
be in off state. Thus, it will have an output
of low
Output of this gate is only the opposite of
the CMOS NAND gate as said in the
previous topic. This will only have an output
of high if the inputs are both low.
CMOS NOR Gate
CMOS NOR gate is also formed by adding a
PMOS and an NMOS to an inverter, as
shown in the figure.
CMOS SET-CLEAR FF

To form a Set-Clear latch, two CMOS NOR

gates or NAND gates is needed. For
converting it to clocked D and J-K flip-flops,
there will be an additional circuits.
8.10 CMOS SERIES
CHARACTERISTICS
The CMOS family of integrated circuits
competes directly with TTL in the small- and
medium-scale integration (SSI, MSI) areas.
CMOS technology has produced better and
better performance characteristics.

CMOS ICs provide several special-purpose

functions not provided by TTL. These are the
few terms that are used when ICs from
different families are to be used together or
as replacements for one another:
Pin-compatible when pin configurations
are the same.
Functionally equivalent when the logic
functions they perform are exactly the
same.
Electrically compatible. when they can be
directly to each other without taking any
special measures.
CMOS Series
Pin- Electrically- Funtionally
Column1 Characteristics
compatible compatible equivalent

very low power dissipation,

4000/14000 Series NO NO
slow compared to TTL

same as those of the 4000

74C Series YES NO
series
has a tenfold increase in
switching
74HC/HCT
speed compared to 74C
(High-Speed YES YES ONLY 74HCT
series,
CMOS)
much higher current
capability

74AC/ACT referred as ACL for advanced

NO ONY 74ACT YES
(Advanced CMOS) CMOS logic

74AHC/AHCT
faster, lower-power, low drive
(Advanced High- YES YES
applications
Speed CMOS)
BiCMOS 5-VOLT LOGIC

Several IC manufacturers have developed

logic series that combine the best features
of bipolar and CMOS logic called BiCMOS
logic. The low-power characteristics of
CMOS and the High-speed characteristics of
bipolar circuits are integrated to produce an
extremely low-power, high-speed logic
family.
POWER SUPPLY VOLTAGE
The 4000/14000 series and 74C series will
operate with VDD values ranging from 3
15 V, which makes them ery versatile. They
can be used in low-voltage battery-
operated circuits, in standard 5-V circuits,
and in circuits where a higher supply
voltage is used to attain the noise margins
required for operation in a high-noise
environment.
FAN-OUT
Like N-MOS and P-MOS, CMOS inputs have
an extremely large resistance that draws
essentially no current from the signal
source. Each CMOS input, however,
typically presents a 5-pF load to ground.
8.11 LOW-VOLTAGE
TECHNOLOGY
IC manufacturers are continually looking for
ways to put semiconductor devices closer
together on a chip, that is, to increase the
chip density. This higher density has at
least two major benefits. First, it allows
more circuits than to be packed onto the
chip; second, with the circuits closer
together, the time for signals to propagate
from one circuit to another will decrease,
thereby improving overall circuit operating
speed.
8.12 OPEN-COLLECTOR/OPEN-DRAIN
OUTPUTS

There are situations in which several digital

devices must share the use of the single
wire in order to transmit a signal to some
destination device, very much like several
neighbors sharing the same street. This
means that several devices must have their
outputs connected to the same wire which
essentially connects them all to each other.
Two outputs contending for control
of a wire.
Totem-pole outputs tied together can
produce harmful current through Q4.
If the two devices where TTL totem-pole outputs, as
similar situation would occur but with different results
because of the difference in output circuitry. Suppose
that Gate A output is in the high state and the Gate B
output is in the low state. In this situation Qab is a very
low resistance load on Q3a and will draw a current that
is far greater than it is rated to handle.
OPEN-COLLECTOR/OPEN-DRAIN
OUTPUTS
One solution to the problem of sharing a
common wire among gates is to remove
the active pull-up transistor from each
gates output circuit. In this way none of
these gates will ever try to assert a logic
high. CMOS output circuits that have been
modified in this way are called open-drain
outputs.
8.13 Tristate Logic
Outputs
It is commonly used in TTL and CMOS as
output circuitry. It is called tristate since it
has three possible outputs: HIGH, LOW and
high-impedance Z (Hi-Z). This device has
an enable input (E) which determine its
operation. When E = 1 , tristate acts as
inverter, otherwise the circuit will be
disabled.
HIGH and LOW
Since, Enable is equal to 1 (E=OE=1), the
circuit will operate as inverter. If the input is
LOW, then its output will be HIGH or from
the Positive voltage. When you input a
HIGH then the device will produce an
output of LOW coming from the ground.
High impedance (Hi-Z)
It happen when the enable= 0 or disabled.
The device does not operate as HIGH or
Low but rather produces a HIGH impedance
at the output since it is an open circuit from
both Source Voltage and ground.
Advantage
Tristate outputs can be connected together
in bus wire without sacrificing its switching
speed, since it acts as totem pole in TTL or
an active pull-up/pull-down in CMOS.
However, we must put in mind that only
one should be enabled at a time, otherwise
tristate output could fight for the control of
the common wire.
Tristate Buffers
Tristate Buffers is a circuit controller of
signal passing from input to output.
Types
Inverting Tristate Buffers inverts the
signal while it pass through the device.
NonInverting Tristate Buffers does not
invert the signal.
The figure above is both non-inverting
tristate buffers. However, there is a
difference between the two; the active state
of their enable. 74LS125 only allows the
signal to pass through when E = 0. On the
other hand, 74LS126, allows it when E=1.
Tristate buffers are very significant in
circuits where several signals are
connected in wire buses. It allows us to
send the appropriate signal by enabling the
right buffer.
For example, when three tristate buffers
are connected in a single bus line, then we
must selsct the right buffer to transmit a
certain signal. When Input Signal B is
needed then, buffer B must also be
activated while the two other buffers must
be disabled. If two or more buffers are
activated, the tendency is that signals will
mix up (bus contention) or could produce
damaging current to the circuit.
Typical IEEE/ANSI symbol for
Tristate
8.14 High- Speed Bus
Interface Logic
Most of the digital system use a bus line to transfer signals to different
components at a hiher speed. However, there are problems arising in bus
line when it becomes a transmission line where physical components are 4
inches or more away from each other since transmissions line has
inductance, capacitance and resistance that may distort the signal during
transmission. The following are typical ways to combat such problems.
Using Resistor, typically 50 ohm, at the end of transmission line may reduce
the reflected pilse waves but it will also require high current to maintain
logic levels voltages.
Capacitor may be used the block the dc current but acts as resistor during
rising and falling ong of signals.
Voltage divider is another method wherein the resistance is larger to the line
impedance, however, with many bus lines, it will become a heavy burden to
the power supply of the system.
Using diode will simply clips off or clamps off the overshoot and undershoot
of the ringing caused by the LC nature of the line.
A series termination or putting a resistor in the source will improve the
reliability of the bus signals but reduce the frequency limits of the bus
Gunning Transceiver Logic Plus (GTLP) is a
bus interface device that are capable to
drive relatively long buses.
Low-Voltage Differential Signalling (LVDS) it
respond only to difference of signal
between the two wires. Its advantage is
that unwanted signals present in the two
lines wont have a significant effect since
only the difference of the signal is needed.
8.15 The ECL Digital IC
Family
Emitter-coupled Logic or Current-mode logic is
developed primarily to prevent limited switching
speed present in typical TTL family. It operates
on the idea that a fixed bias current less than the
collector current saturation (Icsat) is switched to
another collector.
It is essentially a differential amplifier. V EE
supplies a fixe bias current at emitter. V in will
determine in which transistor this current will
flow. If Vin is -1.7V or logic 0 in ECL, the current
will flow to Q2, . If Vin is -0.9V or logic 1, it will flow
in Q1 as shown in the table.
ECL NOR/OR Gate

To create an ECL NOR/OR gate, the circuit

must be expanded in a way that another r
transistor must be paralleled to Q1. In that
case, Q1 and Q3 may be used to switched
out Q2 creating two outputs that are
basically an OR and NOR function.
ECL Characteristics
ECL never saturates and has very high switching speed
which make them faster to any TTL or CMOS gates.
Its nominal levels are -0.8V (Logic 1) and -1.7V (Logic
0)
Worst case ECL noise margins are typically 150 mv and
are not suitable for heavy industrial environments.
It typically produces an output and its complement that
makes the use of inverter unnecessary.
Typical fan out is 25 and power dissipation of 25mW.
It has constant current flow even in switching
transitions which make its beneficial since it does not
generate noise spikes.
8.16 CMOS TRANSMISSION GATE
(BILATERAL SWITCH)
It is basically a single pole, single throw
switch that allows the transmission of signals
in both directions. The diagram below shows
a basic configuration of bilateral switch.
PMOSFET and NMOSFET are parallel to each
other to switch both polarities. CONTROL is
the one responsible for switching on and off
the MOSFET. When CONTROL = HIGH then
both MOSFET are in conduction state,
otherwise it is open. It is called bilateral due
to input and output can be interchanged.
A 4016 quad bilateral switch IC is one
example, in which each switch has
independent controls. Its input and output
can also be interchanged as described
above.
8.17 IC Interfacing
Interfacing means connecting the output of
ones circuit or system to the input of
another circuit or system that has different
electrical characteristics.
Interface circuit is a circuit connected
between the driver and the load, its
function is to take the driver output signal
and condition it so that it is compatible with
the requirements of the load.
 The high state of the CMOS output is enough to drive directly
a TTL input into high state without problems. The low state
could though could cause malfunctions in some cases. Is it
possible to sink a TTL input current into low state without
exceeding the maximum value of the TTL low state input
voltage? Typical CMOS gates are specified to sink about 0.4
mA in the low state while maintaining an output voltage of
0.4 volts or less, sufficient to drive two LS TTL inputs or one
Schottky input, but insufficient to drive standard TTL. In this
case, a 4041 buffer should be used to eliminate this problem
Another solution is to use a voltage level-
translator which defined as devices that
resolve mixed voltage incompatibility
between different parts of a system that
operate in multiple voltage domains.
8.18 TTL Driving CMOS

In interfacing ICs, one must check that the

driving device can meet the current and voltage
requirements of the load device. By the use of a
pull-up resistor it will match the output of the TTL
to the input voltage of the CMOS. Hence providing
and adequate CMOS input voltage level.
8.19 CMOS Driving TTL
CMOS Driving in the HIGH State
By looking at the datasheets of common CMOS devices the can
supply more than enough current to meet the input current
requirements of a TTL, thus making no special considerations in the
HIGH state.
High-Voltage CMOS Driving TTL
Some IC manufacturers have produced several 74LS TTL devices that
can withstand input voltages as high as 15V. These devices can be
driven directly from CMOS outputs operating at V DD = 15V. Since
most TTL cant handle voltages more than 7V before becoming
damaged, and so an interface is necessary if they are to be driven
into a high-voltage CMOS.
Analog Voltage Comparator
A circuit that compares two voltages. If the voltage on the (+) is
greater than the voltage on the (-), the output is HIGH, otherwise its
LOW. The inputs to a comparator can be thought of as analog inputs
but the outputs are always either HIGH or LOW.
 An example of an application of a voltage comparator the LM339 that
contains four voltage comparators.
8.20 Troubleshooting
Logic Pulser
A Logic Pulser is a testing and
troubleshooting tool that generates a short-
duration pulse when manually actuated,
usually by pressing a push button.
Using Logic Pulser and Probe to test
a Circuit
A logic pulser can be used to inject a pulse
or a series of pulses manually into a circuit
to test the circuits response. A logic probe
is almost always used to monitor the
circuits response to the logic pulser.
Which it can also be used to find Nodes
that are shorted directly to the ground or
VCC.
Current Tracer
A current traceris a circuittracerfor
locating and tracing electrical wires,
breakers, neutrals, and ground lines in
industrial settings.
It can detect a changing current in a wire or
printed circuit board trace without breaking
the circuit. It has insulated tip that contains
a magnetic pickup coil