The 8085 Microprocessor

MICROPROCESSOR
Amicroprocessorincorporates the functions of
acomputer'scentral processing unit(CPU) on a
singleintegrated circuit(IC), or at most a few
integratedcircuits.
It is a multipurpose,programmabledevice that
acceptsdigital data as input, processes it according to
instructionsstoredinitsmemory,andprovidesresults
as output. It is an example of sequential digital logic,
asithasinternalmemory.Microprocessorsoperateon
numbers and symbols represented in thebinary
numeralsystem.
TheIntel 8085is an8-bitmicroprocessorintroduced
byIntelin1977. 2
Block diagram of microprocessor

Microprocessor
INPUT As OUTPUT
CPU

MEMORY

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4
 Processor System Architecture
The typical processor system consists of:
CPU (central processing unit)
ALU (arithmetic-logic unit)
Control Logic
Registers, etc
Memory
Input / Output interfaces

Interconnections between these units:

Address Bus
Data Bus
Control Bus

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6
 The 8085: CPU Internal Structure

The internal architecture of the 8085 CPU is capable of performing the following
operations:

Store8-bitdata(Registers,Accumulator)

Performarithmeticandlogicoperations(ALU)

Testforconditions(IF/THEN)

Sequencetheexecutionofinstructions

StoretemporarydatainRAMduringexecution

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The 8085: CPU Internal Structure

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The 8085: Registers

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 The 8085: CPU Internal Structure

Registers

Six general purpose 8-bit registers: B, C, D, E, H, L

They can also be combined as register pairs to

perform 16-bit operations: BC, DE, HL

Registers are programmable (data load, move, etc.)

Accumulator

Single 8-bit register that is part of the ALU !

Used for arithmetic / logic operations the result is always stored in

the accumulator.
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 The 8085: CPU Internal Structure

The Program Counter (PC)

This is a register that is used to control the sequencing of the execution of
instructions.
This register always holds the address of the next instruction.
Since it holds an address, it must be 16 bits wide.
The Stack pointer
The stack pointer is also a 16-bit register that is used to point into memory.
The memory this register points to is a special area called the stack.
The stack is an area of memory used to hold data that will be retreived soon.
The stack is usually accessed in a Last In First Out (LIFO) fashion.

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The 8085 and Its Busses
The 8085 is an 8-bit general purpose microprocessor that can
address 64K Byte of memory.
It has 40 pins and uses +5V for power. It can run at a maximum
frequency of 3 MHz.
The pins on the chip can be grouped into 6 groups:
Address Bus.
Data Bus.
Control and Status Signals.
Power supply and frequency.
Externally Initiated Signals.
Serial I/O ports.

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 The 8085 Bus Structure

The 8-bit 8085 CPU (or MPU Micro Processing Unit) communicates with the other units
using a 16-bit address bus, an 8-bit data bus and a control bus.

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The Address and Data Busses
The address bus has 8 signal lines A8 A15 which are
unidirectional.
The other 8 address bits are multiplexed (time shared) with the 8
data bits.
So, the bits AD0 AD7 are bi-directional and serve as A0
A7 and D0 D7 at the same time.
During the execution of the instruction, these lines carry
the address bits during the early part, then during the
late parts of the execution, they carry the 8 data bits.
In order to separate the address from the data, we can use a
latch to save the value before the function of the bits
changes.

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The Control and Status Signals
There are 4 main control and status signals. These are:
ALE: Address Latch Enable. This signal is a pulse that
become 1 when the AD0 AD7 lines have an address on
them. It becomes 0 after that. This signal can be used to
enable a latch to save the address bits from the AD lines.
RD: Read. Active low.
WR: Write. Active low.
IO/M: This signal specifies whether the operation is a
memory operation (IO/M=0) or an I/O operation
(IO/M=1).
S1 and S0 : Status signals to specify the kind of
operation being performed .Usually un-used in small
systems.
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Frequency Control Signals
There are 3 important pins in the frequency control group.
X0 and X1 are the inputs from the crystal or clock generating
circuit.
The frequency is internally divided by 2.
So, to run the microprocessor at 3 MHz, a clock running
at 6 MHz should be connected to the X0 and X1 pins.

CLK (OUT): An output clock pin to drive the clock of the rest of the
system.

We will discuss the rest of the control signals as we get to them.

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The ALU
In addition to the arithmetic & logic circuits, the ALU
includes the accumulator, which is part of every
arithmetic & logic operation.

Also, the ALU includes a temporary register used for

holding data temporarily during the execution of the
operation. This temporary register is not accessible by
the programmer.

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The Flags register
There is also the flags register whose bits are affected by the arithmetic &
logic operations.
S-sign flag
The sign flag is set if bit D7 of the accumulator is set after an
arithmetic or logic operation.
Z-zero flag
Set if the result of the ALU operation is 0. Otherwise is reset. This
flag is affected by operations on the accumulator as well as other
registers. (DCR B).
AC-Auxiliary Carry
This flag is set when a carry is generated from bit D3 and passed
to D4 . This flag is used only internally for BCD operations.
(Section 10.5 describes BCD addition including the DAA
instruction).
P-Parity flag
After an ALU operation if the result has an even # of 1s the p-
flag is set. Otherwise it is cleared. So, the flag can be used to
indicate even parity.
CY-carry flag
Discussed earlier
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More on the 8085 machine
cycles
The 8085 executes several types of instructions with each
requiring a different number of operations of different types.
However, the operations can be grouped into a small set.
The three main types are:
Memory Read and Write.
I/O Read and Write.
Request Acknowledge.

These can be further divided into various operations (machine

cycles).

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Opcode Fetch Machine Cycle
The first step of executing any instruction is the Opcode fetch cycle.
In this cycle, the microprocessor brings in the instructions Opcode
from memory.
To differentiate this machine cycle from the very similar
memory read cycle, the control & status signals are set as
follows:
IO/M=0, s0 and s1 are both 1.
This machine cycle has four T-states.
The 8085 uses the first 3 T-states to fetch the opcode.
T4 is used to decode and execute it.
It is also possible for an instruction to have 6 T-states in an opcode
fetch machine cycle.

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Memory Read Machine Cycle
The memory read machine cycle is
exactly the same as the opcode fetch
except:
It only has 3 T-states
The s0 signal is set to 0 instead.

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The Memory Read Machine
Cycle
To understand the memory read machine cycle, lets study the
execution of the following instruction: 2000H 3E
MVI A, 32
2001H 32
In memory, this instruction looks like:
The first byte 3EH represents the opcode for loading a byte into
the accumulator (MVI A), the second byte is the data to be
loaded.
The 8085 needs to read these two bytes from memory before it can
execute the instruction. Therefore, it will need at least two machine
cycles.
The first machine cycle is the opcode fetch discussed earlier.
The second machine cycle is the Memory Read Cycle.
Figure 3.10 page 83.

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Machine Cycles vs. Number of bytes in the instruction
Machine cycles and instruction length, do not have a direct relationship.
To illustrate lets look at the machine cycles needed to execute the following
instruction.
STA 2065H
This is a 3-byte instruction requiring 4 machine cycles and 13 T-states.
The machine code will be stored
in memory as shown to the right
This instruction requires the following 4 machine cycles:
Opcode fetch to fetch the opcode (32H) from location 2010H,
decode it and determine that 2 more bytes are needed (4 T-states).
Memory read to read the low order byte of the address (65H) 32H(3 T-2010H
states). 65H 2011H

Memory read to read the high order byte of the address (20H)20H (3 T-
2012H
states).
A memory write to write the contents of the accumulator into the
memory location.

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 Memory Types
ROM
PROM
EPROM
EEPROM
RAM

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The Memory Write Operation
In a memory write operation:
The 8085 places the address (2065H) on the
address bus
Identifies the operation as a memory write
(IO/M=0, s1=0, s0=1).
Places the contents of the accumulator on the data
bus and asserts the signal WR.
During the last T-state, the contents of the data
bus are saved into the memory location.

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Memory interfacing
There needs to be a lot of interaction between the
microprocessor and the memory for the exchange of
information during program execution.
Memory has its requirements on control signals
and their timing.
The microprocessor has its requirements as well.

The interfacing operation is simply the matching of

these requirements.

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Memory structure & its requirements
ROM
Data Lines

RAM
Input Buffer WR

Address CS Address CS
Lines Lines

Output Buffer RD Output Buffer RD

Data Lines
Date
Lines

The process of interfacing the above two chips is the

same.
However, the ROM does not have a WR signal.

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Interfacing Memory
Accessing memory can be summarized into the following three
steps:
Select the chip.
Identify the memory register.
Enable the appropriate buffer.

Translating this to microprocessor domain:

The microprocessor places a 16-bit address on the address
bus.
Part of the address bus will select the chip and the other
part will go through the address decoder to select the
register.
The signals IO/M and RD combined indicate that a
memory read operation is in progress. The MEMR signal
can be used to enable the RD line on the memory chip.

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Address decoding
The result of address decoding is the identification of
a register for a given address.
A large part of the address bus is usually
connected directly to the address inputs of the
memory chip.
This portion is decoded internally within the chip.
What concerns us is the other part that must be
decoded externally to select the chip.
This can be done either using logic gates or a
decoder.

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The Overall Picture
Putting all of the concepts together, we
get:
Chip Selection
A15-A10 Circuit

8085
CS
A15-A8


ALE
A9-A0 1K Byte
AD7-AD0 Latch Memory
A7-A0 Chip

WR RD IO/M D7-D0
RD WR

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 8085 Instruction Set
Data transfer operations

Between registers
Between memory location and a register
Direct write to a register / memory
Between I/O device and accumulator

Arithmetic operations (ADD, SUB, INR, DCR)

Logic operations

Branching operations (JMP, CALL, RET)

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8085 Instruction Types

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8085 Instruction Types

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8085 Instruction Types

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 Simple Data Transfer Operations

Examples:

MOV B,A 47 FromACCtoREG

MOV C,D 4A BetweentwoREGs
MVI D,47 16Direct-writeintoREGD
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Simple Data Transfer Operations

Example:

OUT05 D3
05

ContentsofACCsenttooutputportnumber05.

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Simple Memory Access Operations

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Simple Memory Access Operations

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Arithmetic Operations

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Arithmetic Operations

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Arithmetic Operations

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Overview of Logic Operations

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Logic Operations

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Logic Operations

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Logic Operations

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 Branching Operations

Note: Thisisanunconditionaljumpoperation.
Itwillalwaysforcetheprogramcountertoafixed
memoryaddresscontinuousloop!

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 Branching Operations

Conditionaljumpoperationsareveryusefulfor
decisionmakingduringtheexecutionoftheprogram.

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Direct Memory Access Operations

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Direct Memory Access Operations

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Indirect Memory Access Operations

Use a register PAIR as an address pointer !

We can define memory access operations using the memory location (16 bit address)
stored in a register pair: BC, DE or HL.

First, we have be able to load the register pairs.

LXI B, (16-bit address)

LXI D, (16-bit address)
LXI H, (16-bit address)

We can also increment / decrement register pairs.

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Loading Register Pairs

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 Interrupts in 8085

In many real-time operations, the microprocessor should be able to receive an

external asynchronous signal (interrupt) while it is running a routine.

When the interrupt signal arrives:

Theprocessorwillbreakitsroutine

Gotoadifferentroutine(serviceroutine)

Completetheserviceroutine

Gobacktotheregularroutine

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 Interrupts in 8085

In order to execute an interrupt routine, the processor:

Shouldbeabletoacceptinterrupts(interruptenable)

Savethelastcontentoftheprogramcounter(PC)

Knowwheretogoinprogrammemorytoexecute
theserviceroutine

Telltheoutsideworldthatitisexecutinganinterrupt

GobacktothesavedPClocationwhenfinished.

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 Vectored Interrupts

There are four other interrupt inputs in 8085 that

transfer the operation immediately to a specific address:

TRAP:goto0024

RST7.5:goto 003C
RST6.5 0034
RST5.5 002C

RST7.5,RST6.5andRST5.5aremaskableinterrupts, theyare
acknowledgedonlyiftheyarenotmasked!

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Vectored Interrupts

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SIM: Set Interrupt Mask

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 Machine Language
Thenumberofbitsthatformthewordofamicroprocessor
isfixedforthatparticularprocessor.
These bits define a maximum number of combinations. For
example an 8-bit microprocessor can have at most 28 = 256
differentcombinations.
However, in most microprocessors, not all of these
combinationsareused.
Certain patterns are chosen and assigned specific
meanings.
Each of these patterns forms an instruction for the
microprocessor.
The complete set of patterns makes up the
microprocessorsmachinelanguage.
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The 8085 Machine Language
The8085(fromIntel)isan8-bitmicroprocessor.
The8085usesatotalof246bitpatternstoformitsinstruction
set.
These246patternsrepresentonly74instructions.
The reason for the difference is that some (actually most)
instructionshavemultipledifferentformats.
Because it is very difficult to enter the bit patterns correctly,
theyareusuallyenteredinhexadecimalinsteadofbinary.
Forexample,thecombination00111100whichtranslatesinto
incrementthenumberintheregistercalledtheaccumulator,
isusuallyenteredas3C.

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 Assembly Language
Entering the instructions using hexadecimal is quite
easierthanenteringthebinarycombinations.
However, it still is difficult to understand what a
programwritteninhexadecimaldoes.
So, each company defines a symbolic code for the
instructions.
Thesecodesarecalledmnemonics.
The mnemonic for each instruction is usually a group
oflettersthatsuggesttheoperationperformed.

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 Assembly Language
Usingthesameexamplefrombefore,
00111100 translates to 3C in hexadecimal
(OPCODE)
Itsmnemonicis:INRA.
INR stands for increment register andAis short
foraccumulator.
Anotherexampleis:
10000000,Whichtranslatesto80inhexadecimal.
ItsmnemonicisADDB.
Add register B to the accumulator and keep the
resultintheaccumulator. 60
 Assembly Language
It is important to remember that a machine
languageanditsassociatedassemblylanguage
arecompletelymachinedependent.
In other words, they are not transferable from one
microprocessortoadifferentone.
For example, Motorolla has an 8-bit
microprocessorcalledthe6800.
The 8085 machine language is very different from
thatofthe6800.Soistheassemblylanguage.
Aprogramwrittenforthe8085cannotbeexecuted
onthe6800andviceversa.
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Assembling The Program
How does assembly language get translated into
machinelanguage?Therearetwoways:
1st there is hand assembly. The programmer
translates each assembly language instruction into
its equivalent hexadecimal code (machine
language). Then the hexadecimal code is entered
intomemory.
The other possibility is a program called an
assembler, which does the translation
automatically.

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Machine Control Instructions

These instructions affect the operation of

the processor. For e.g.
HLT Stop program execution
NOP Do not perform any operation

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Writing a Assembly Language Program

Steps to write a program

Analyze the problem
Develop program Logic
Write an Algorithm
Make a Flowchart
Write program Instructions using
Assembly language of 8085
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 Program 8085 in Assembly language to add two 8-
bit numbers and store 8-bit result in register C.
1. Analyze the problem
Addition of two 8-bit numbers to be done
2. Program Logic
Add two numbers
Store result in register C
Example
10011001 (99H) A
+00111001 (39H) D
11010010 (D2H) C
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 Translationto8085
3. Algorithm operations
1. Get two numbers Load 1st no. in register D
Load 2nd no. in register E
2. Add them CopyregisterDtoA
AddregisterEtoA
3. Store result CopyAtoregisterC
4. Stop Stopprocessing

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 4. Make a Flowchart
Start
Load1stno.inregisterD
Load Registers D, E Load2ndno.inregisterE

Copy D to A CopyregisterDtoA
AddregisterEtoA
Add A and E

Copy A to C CopyAtoregisterC

Stopprocessing
Stop

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 5. Assembly Language Program
1. Get two numbers
a) Load1stno.inregisterD MVID,2H
b) Load2ndno.inregisterE MVIE,3H
2. Add them
a) CopyregisterDtoA MOVA,D
b) AddregisterEtoA ADDE
3. Store result
a) CopyAtoregisterC MOVC,A
4. Stop
a) Stopprocessing HLT
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 Program 8085 in Assembly language to add two 8-
bit numbers. Result can be more than 8-bits.
1. Analyze the problem
Result of addition of two 8-bit numbers can be
9-bit
Example
10011001 (99H) A
+10011001 (99H) B
100110010 (132H)
The 9th bit in the result is called CARRY bit.

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 How 8085 does it?
Adds register A and B
Stores 8-bit result in A
SETS carry flag (CY) to indicate carry bit

10011001 99H A
+
10011001 99H B

10 10011001
00110010 32H
99H A
C 70
 Storing result in Register memory
C A
Y
1 10011001 32H

Register B Register C

Step-1CopyAtoC
Step-2
a) ClearregisterB
b) IncrementBby1
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2. Program Logic

1. Add two numbers

2. Copy 8-bit result in A to C
3. If CARRY is generated
Handle it
4. Result is in register pair BC

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 Translationto8085
3. Algorithm
operations

1. Load two numbers in Load registers D, E

registers D, E
CopyregisterDtoA
2. Add them
AddregisterEtoA

3. Store 8 bit result in C

CopyAtoregisterC
4. Check CARRY flag
UseConditionalJump
5. If CARRY flag is SET
instructions
Store CARRY in
register B ClearregisterB
IncrementB
6. Stop
Stopprocessing
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 4. Make a Flowchart
Start

Load Registers D, E False

If
Clear B
CARRY
Copy D to A NOT SET
Increment B
True
Add A and E

Copy A to C
Stop

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 5. Assembly Language Program
LoadregistersD,E MVID,2H
MVIE,3H
CopyregisterDtoA
AddregisterEtoA MOVA,D
CopyAtoregisterC ADDE
MOVC,A
UseConditionalJump
JNCEND
instructions
ClearregisterB MVIB,0H
IncrementB INRB
Stopprocessing END: HLT
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 Stack Memory
Growsbackwardsintomemory.
Bettertoplacethebottomofthestackattheendof
memory.
To keep it as far away from user programs as
possible.
Stack is defined by setting the SP (Stack Pointer)
register.
LXISP,FFFFH
ThissetsSPtolocationFFFFH(endofmemoryfor
8085).

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 Call by References
If SR performs operations on the contents
oftheregisters.
These modifications will be transferred
backtothecallingprogramuponreturning
fromasubroutine.
Ifthisisnotdesired,theSRshouldPUSH
registersandPOPonreturn.

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 An Example I/O Device
Keyboard
Keyboardcontrollerscansandreports
Keydepressionsandreleases
Supplieskeyidentityasascancode
Scancodeislikeasequencenumberofthekey
Keysscancodedependsonitspositiononthe
keyboard
NorelationtotheASCIIvalueofthekey

Interfacedthroughan8-bitparallelI/Oport
Originallysupportedby8255programmable
peripheralinterfacechip(PPI)

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An Example I/O Device (contd)
8255PPIhasthree8-bitregisters
PortA(PA)
PortB(PB)
PortC(PC)
Theseportsaremappedasfollows
8255register Portaddress
PA(inputport) 60H
PB(outputport) 61H
PC(inputport) 62H
Commandregister 63H
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An Example I/O Device (contd)
Mappingof8255I/Oports

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An Example I/O Device (contd)
MappingI/Oportsissimilartomappingmemory
Partialmapping
Fullmapping
Keyboardscancodeandstatuscanbereadfromport
60H
7-bitscancodeisavailablefrom
PA0PA6
KeystatusisavailablefromPA7
PA7=0keydepressed
PA0=1keyreleased

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 I/O Data Transfer
Datatransferinvolvestwophases
Adatatransferphase
Itcanbedoneeitherby
ProgrammedI/O
DMA
Anend-notificationphase
ProgrammedI/O
Interrupt
Threebasictechniques
ProgrammedI/O
DMA
Interrupt-drivenI/O

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I/O Data Transfer (contd)
ProgrammedI/O
Donebybusy-waiting
Thisprocessiscalledpolling
Example
Readingakeyfromthekeyboardinvolves
WaitingforPA7bittogolow
Indicatesthatakeyispressed
Readingthekeyscancode
TranslatingittotheASCIIvalue
Waitinguntilthekeyisreleased

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 I/O Data Transfer (contd)
Directmemoryaccess(DMA)
ProblemswithprogrammedI/O
Processorwastestimepolling
Inourexample
Waitingforakeytobepressed,
Waitingforittobereleased
Maynotsatisfytimingconstraintsassociated
withsomedevices
Diskreadorwrite
DMA
Freestheprocessorofthedatatransfer
responsibility
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I/O Data Transfer (contd)

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Interfacing Analog to Digital
Data Converters
Inmostofthecases,thePIO8255isusedforinterfacingthe
analogtodigitalconverterswithmicroprocessor.
Theanalogtodigitalconvertersistreadedasaninputdeviceby
themicroprocessor,thatsendsaninitialisingsignaltotheADCto
starttheanalogytodigitaldataconversationprocess.Thestartof
conversationsignalisapulseofaspecificduration.
Theprocessofanalogtodigitalconversionisaslowprocess,and
themicroprocessorhastowaitforthedigitaldatatillthe
conversionisover.Aftertheconversionisover,theADCsends
endofconversionEOCsignaltoinformthemicroprocessorthat
theconversionisoverandtheresultisreadyattheoutputbuffer
oftheADC.ThesetasksofissuinganSOCpulsetoADC,reading
EOCsignalfromtheADCandreadingthedigitaloutputofthe
ADCarecarriedoutbytheCPUusing8255I/Oports.
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Interfacing Analog to Digital
Data Converters
ThetimetakenbytheADCfromthe
activeedgeofSOCpulsetilltheactive
edgeofEOCsignaliscalledasthe
conversiondelayoftheADC.
Itmayrangeanywherefromafew
microsecondsincaseoffastADCto
evenafewhundredmillisecondsincase
ofslowADCs.
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 General algorithm for ADC
interfacing
1. Ensurethestabilityofanaloginput,appliedtotheADC.
2. IssuestartofconversionpulsetoADC
3. Readendofconversionsignaltomarktheendofconversion
processes.
4. ReaddigitaldataoutputoftheADCasequivalentdigitaloutput.
5. AnaloginputvoltagemustbeconstantattheinputoftheADC
rightfromthestartofconversiontilltheendoftheconversionto
getcorrectresults.Thismaybeensuredbyasampleandhold
circuitwhichsamplestheanalogsignalandholdsitconstantfor
aspecifictimeduration.Themicroprocessormayissueahold
signaltothesampleandholdcircuit.
6. Iftheappliedinputchangesbeforethecompleteconversion
processisover,thedigitalequivalentoftheanaloginput
calculatedbytheADCmaynotbecorrect.
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 ADC 0808/0809
Theanalogtodigitalconverterchips0808and0809are8-bit
CMOS,successiveapproximationconverters.
Thistechniqueisoneofthefasttechniquesforanalogtodigital
conversion.Theconversiondelayis100sataclockfrequencyof
640KHz,whichisquitelowascomparedtootherconverters.
Theseconvertersdonotneedanyexternalzeroorfullscale
adjustmentsastheyarealreadytakencareofbyinternalcircuits.
Theseconvertersinternallyhavea3:8analogmultiplexersothat
atatimeeightdifferentanalogconversionbyusingaddresslines
-ADDA,ADDB,ADDC.Usingtheseaddressinputs,
multichanneldataacquisitionsystemcanbedesignedusinga
singleADC.TheCPUmaydrivetheselinesusingoutputport
linesincaseofmultichannelapplications.Incaseofsingleinput
applications,thesemaybehardwiredtoselecttheproperinput.
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Interfacing Digital To Analog
Converters
Thedigitaltoanalogconvertersconvertbinarynumberintotheir
equivalentvoltages.TheDACfindapplicationsinareaslike
digitallycontrolledgains,motorsspeedcontrols,programmable
gainamplifiersetc.
AD75238-bitMultiplyingDAC:Thisisa16pinDIP,
multiplyingdigitaltoanalogconverter,containingR-2Rladder
forD-AconversionalongwithsinglepoledoublethrownNMOS
switchestoconnectthedigitalinputstotheladder.

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