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# VLSI

Design

## CMOS Transistor Theory

Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models

## EE 447 VLSI Design

3: CMOS Transistor T 2
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships

## Transistor gate, source, drain all have capacitance

I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed

## EE 447 VLSI Design

3: CMOS Transistor T 3
MOS Capacitor
Gate and body form MOS capacitor
Operating modes polysilicon gate
Vg < 0
silicon dioxide insulator
Accumulation +
- p-type body

Depletion (a)

## Inversion 0 < Vg < V t

depletion region
+
-

(b)

Vg > Vt
Example with an NMOS +
inversion region
depletion region
capacitor -

(c)

## EE 447 VLSI Design

3: CMOS Transistor T 4
Terminal Voltages
Vg
Mode of operation depends on Vg, Vd, Vs
+ +
Vgs = Vg Vs Vgs Vgd
- -
Vgd = Vg Vd
Vs Vd
- +
Vds = Vd Vs = Vgs - Vgd Vds

## Source and drain are symmetric diffusion terminals

However, Vds 0
NMOS body is grounded. First assume source may be
grounded or may be at a voltage above ground.
Three regions of operation
Cutoff
Linear
Saturation

## EE 447 VLSI Design

3: CMOS Transistor T 5
nMOS Cutoff
Let us assume Vs = Vb
No channel, if Vgs = 0
Ids = 0 Vgs = 0
g
Vgd
+ +
- -
s d

n+ n+

p-type body
b

## EE 447 VLSI Design

3: CMOS Transistor T 6
NMOS Linear
Channel forms if Vgs > Vt
Vgs > Vt
No Currernt if Vds = 0 + g +
Vgd = Vgs

- -
s d
n+ n+ Vds = 0

p-type body
b

Linear Region:
Vgs > Vt
Vgs > Vgd > Vt
If Vds > 0, Current flows + g +
- - Ids
from d to s ( e- from s to d) s d

0 < Vds < Vgs-Vt

## with Vds if Vds > Vgs Vt. p-type body

b
Similar to linear resistor

## EE 447 VLSI Design

3: CMOS Transistor T 7
NMOS Saturation
Channel pinches off if Vds > Vgs Vt.
Ids independent of Vds, i.e., current saturates
Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

## EE 447 VLSI Design

3: CMOS Transistor T 8
I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel
How fast is the charge moving

## EE 447 VLSI Design

3: CMOS Transistor T 9
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide (dielectric) channel

Qchannel =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

## EE 447 VLSI Design

3: CMOS Transistor T 10
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel

Qchannel = CV
C=

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

## EE 447 VLSI Design

3: CMOS Transistor T 11
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel

Qchannel = CV
C = Cg = oxWL/tox = CoxWL Cox = ox / tox
V = Vgc Vt = (Vgs Vds/2) Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

## EE 447 VLSI Design

3: CMOS Transistor T 12
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E = Vds/L
Time for carrier to cross channel:
t=L/v

## EE 447 VLSI Design

3: CMOS Transistor T 13
NMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
Qchannel
I ds
t
W V V Vds V
Cox gs t ds
L 2
W
= Cox
Vgs Vt ds Vds
V
2 L

## EE 447 VLSI Design

3: CMOS Transistor T 14
NMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases
current

I ds Vgs Vt
Vdsat
2 Vdsat

Vgs Vt
2

## EE 447 VLSI Design

3: CMOS Transistor T 15
NMOS I-V Summary
Shockley 1st order transistor models (valid for
Large channel devices only)

0 Vgs Vt cutoff

I ds Vgs Vt ds Vds Vds Vdsat
V
linear
2

Vgs Vt
2
Vds Vdsat saturation
2

## EE 447 VLSI Design

3: CMOS Transistor T 16
Example
For a 0.6 m process (MOSIS site)
From AMI Semiconductor
2.5
tox = 100 Vgs = 5

2
= 350 cm2/V*s
Vt = 0.7 V 1.5 Vgs = 4

Ids (mA)
Plot Ids vs. Vds 1
Vgs = 3
Vgs = 0, 1, 2, 3, 4, 5 0.5
Vgs = 2
Use W/L = 4/2 Vgs = 1
0
0 1 2 3 4 5
Vds
W 3.9 8.85 1014 W W
Cox 350 120 A /V 2
L 100 108 L L

## EE 447 VLSI Design

3: CMOS Transistor T 17
PMOS I-V

## All dopings and voltages are inverted for PMOS

Mobility p is determined by holes
Typically 2-3x lower than that of electrons n
120 cm2/V*s in AMI 0.6 m process
Thus PMOS must be wider to provide same current
In this class, assume n / p = 2

## EE 447 VLSI Design

3: CMOS Transistor T 18
Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation

## Source and drain have capacitance to body

Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion

## EE 447 VLSI Design

3: CMOS Transistor T 19
Gate Capacitance
Approximate channel as connected to source
Cgs = oxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/m

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

## EE 447 VLSI Design

3: CMOS Transistor T 20
Diffusion Capacitance
Csb, Cdb
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to Cg
for contacted diff
Cg for uncontacted
Varies with process

## EE 447 VLSI Design

3: CMOS Transistor T 21
Pass Transistors
We have assumed source is grounded
What if source > 0? VDD
VDD
e.g. pass transistor passing VDD

## EE 447 VLSI Design

3: CMOS Transistor T 22
NMOS Pass Transistors
We have assumed source is grounded
What if source > 0? VDD
e.g. pass transistor passing VDD VDD
Let Vg = VDD
Now if Vs > VDD-Vt, Vgs < Vt
Vs
Hence transistor would turn itself off

## NMOS pass transistors pull-up no higher than VDD-Vtn

Approach degraded value slowly (low Ids)

## EE 447 VLSI Design

3: CMOS Transistor T 23
Pass Transistor Ckts

VDD VDD
VDD

VDD

VDD
VSS

## EE 447 VLSI Design

3: CMOS Transistor T 24
Pass Transistor Ckts

## VDD VDD VDD

VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn

VDD
Vs = |Vtp| VDD-Vtn
VDD VDD-2Vtn
VSS

## EE 447 VLSI Design

3: CMOS Transistor T 25
Effective Resistance
Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis

## Simplification: treat transistor as resistor

Replace Ids(Vds, Vgs) with effective resistance R
Ids = Vds/R
R averaged across switching of digital gate
Too inaccurate to predict current at any given time
But good enough to predict RC delay

## EE 447 VLSI Design

3: CMOS Transistor T 26
RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance

Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C

## Capacitance proportional to width

Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k kC
g k g k g
s kC kC
kC s
s
d

## EE 447 VLSI Design

3: CMOS Transistor T 27
RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width
Values similar across many processes
Resistance
R 6 K*m in 0.6um process
Improves with shorter channel lengths

Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesnt matter as long as you are consistent

## EE 447 VLSI Design

3: CMOS Transistor T 28
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter

2 Y 2
A
1 1

## EE 447 VLSI Design

3: CMOS Transistor T 29
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter

2C

2C
2C
2 Y 2
A Y
1 1
C
R C

## EE 447 VLSI Design

3: CMOS Transistor T 30
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter

2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

## EE 447 VLSI Design

3: CMOS Transistor T 31
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC
EE 447 VLSI Design
3: CMOS Transistor T 32