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UNIT-II

BASIC COMPUTER
ORGANIZATION AND DESIGN

U1.
Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63., by Deepali Kamthania
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LEARNING OBJECTIVES
System Bus
Instruction Codes

Computer Registers

Computer Instructions

Timing and Control

Instruction Cycle

Memory Reference Instructions

Input-Output and Interrupt

Complete Computer Description

Design of Basic Computer

Design of Accumulator Logic


Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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STRUCTURE

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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SYSTEM BUSES
The major computer system components (processor, main
memory, I/O modules) need to be interconnected in order to
exchange data and control signals
A bus is a communication pathway connecting two or more
devices
A bus that connects major computer components (processor,
memory, I/O) is called a system bus.
Bus = a shared transmission medium. Only one device at a
time Can successfully transmit.
shared system bus consisting of multiple lines
a hierarchy of buses to improve performance.
Key design elements for buses include: Arbitration,
Timing, width
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SYSTEM BUSES

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MULTIPLE BUS HIERARCHIES
In general, the more devices attached to the bus,
the greater the bus length and hence the greater
the propagation delay.
The bus may become a bottleneck as the
aggregate data transfer demand approaches the
capacity of the bus.

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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SYNCHRONOUS BUSES
Synchronous buses include a clock line between the control
lines, line that is controlled by a clock quartz oscillator,
usually between 5 - 133 MHz
All the transfers on the system bus has a fixed protocol
related to the clock signal, and it is developed along an
integer number of cycles, called bus cycles.
The advantages of a synchronous bus are a high speed of
transfer, the very simple implied logic
The disadvantage comes from transfers that can be shorter
than the time corresponding to the integer number of bus
cycles.

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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INTRODUCTION
Every different processor type has its own design
(different registers, buses, microoperations, machine
instructions, etc)

Modern processor is a very complex device

It contains
Many registers

Multiple arithmetic units, for both integer and floating point


calculations
The ability to pipeline several consecutive instructions to speed
execution etc.

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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INTRODUCTION
However, to understand how processors work, we will
start with a simplified processor model

This is similar to what real processors were like ~25


years ago

M. Morris Mano introduces a simple processor model he


calls the Basic Computer

We will use this to introduce processor organization and


the relationship of the RTL model to the higher level
computer processor

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BASIC COMPUTER
The Basic Computer has two components, a processor and memory

The memory has 4096 words in it


4096 = 212, so it takes 12 bits to select a word in memory

Each word is 16 bits long

CPU RAM
0

15 0

4095

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Instruction codes
INSTRUCTIONS

Program
A sequence of (machine) instructions

(Machine) Instruction
A group of bits that tell the computer to perform a specific
operation (a sequence of micro-operation)
The instructions of a program, along with any needed data are
stored in memory
The CPU reads the next instruction from memory
It is placed in an Instruction Register (IR)
Control circuitry in control unit then translates the instruction
into the sequence of microoperations necessary to implement it

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Instruction codes
INSTRUCTION FORMAT
A computer instruction is often divided into two parts

An opcode (Operation Code) that specifies the


operation for that instruction
An address that specifies the registers and/or locations
in memory to use for that operation

In the Basic Computer, since the memory contains 4096 (=


212) words, we needs 12 bit to specify which memory
address this instruction will use

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Instruction codes
INSTRUCTION FORMAT
In the Basic Computer, bit 15 of the instruction specifies
the addressing mode (0: direct addressing, 1: indirect
addressing)

Since the memory words, and hence the instructions, are


16 bits long, that leaves 3 bits for the instructions opcode
Instruction Format
15 14 12 11 0
I Opcode Address

Addressing
mode

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Instruction codes
ADDRESSING MODES
The address field of an instruction can represent either
Direct address: the address in memory of the data to use (the address of the
operand), or
Indirect address: the address in memory of the address in memory of the
data to use Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand
1350 Operand

+ +
AC AC

Effective Address (EA)


The address, that can be directly used without modification to access an
operand for a computation-type instruction, or as the target address for a
branch-type instruction
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Instruction codes
PROCESSOR REGISTERS
A processor has many registers to hold instructions, addresses,
data, etc
The processor has a register, the Program Counter (PC) that holds
the memory address of the next instruction to get
Since the memory in the Basic Computer only has 4096
locations, the PC only needs 12 bits
In a direct or indirect addressing, the processor needs to keep
track of what locations in memory it is addressing: The Address
Register (AR) is used for this
The AR is a 12 bit register in the Basic Computer
When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The processor
then uses this value as data for its operation
The Basic Computer has a single general purpose register the
Accumulator (AC)
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Instruction codes
PROCESSOR REGISTERS
The significance of a general purpose register is that it can be
referred to in instructions
e.g. load AC with the contents of a specific memory location;
store the contents of AC into a specified memory location
Often a processor will need a scratch register to store
intermediate results or other temporary data; in the Basic
Computer this is the Temporary Register (TR)
The Basic Computer uses a very simple model of input/output
(I/O) operations
Input devices are considered to send 8 bits of character data
to the processor
The processor can send 8 bits of character data to output
devices

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PROCESSOR REGISTERS
The Input Register (INPR) holds an 8 bit character gotten from
an input device
The Output Register (OUTR) holds an 8 bit character to be
send to an output device

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Registers

BASIC COMPUTER REGISTERS


Registers in the Basic Computer
11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of
instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR
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Outputand Register
Management, New Holds
Delhi-63,output
by Dr. Deepali Kamthania U1.
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Registers
COMMON BUS SYSTEM

The registers in the Basic Computer are connected


using a bus
This gives a savings in circuitry over complete
connections between registers

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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Registers
COMMON BUS SYSTEM
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1
LD INR CLR
PC 2
LD INR CLR

DR 3

LD INR CLR
E
ALU AC 4
LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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Registers
COMMON BUS SYSTEM

Read
INPR
Memory Write
4096 x 16
Address E ALU

AC

L I C

L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus


S 0 S1 S2

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Registers
COMMON BUS SYSTEM
Three control lines, S2, S1, and S0 control which register the bus
selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

Either one of the registers will have its load signal activated, or
the memory will have its read signal activated
Will determine where the data from the bus gets loaded
The 12-bit registers, AR and PC, have 0s loaded onto the bus in
the high order 4 bit positions
When the 8-bit register OUTR is loaded from the bus, the data
comes from the low order 8 bits on the bus
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BASIC COMPUTER INSTRUCTIONS

Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)


15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)


15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)


15 12 11 0
1 1 1 1 I/O operation

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BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC


CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC


OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
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INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function
that is known to be computable.

Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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CONTROL UNIT

Control unit (CU) of a processor translates from machine


instructions to the control signals for the microoperations that
implement them
Control units are implemented in one of two ways
Hardwired Control
CU is made up of sequential and combinational circuits to generate
the control signals
Microprogrammed Control
A control memory on the processor contains microprograms that
activate the necessary control signals

We will consider a hardwired implementation of the control


unit for the Basic Computer

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HARDWIRED/MICROPROGRAMMED

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TIMING AND CONTROL

Control unit of Basic Computer


Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)


sequence Clear (CLR)
counter
(SC) Clock

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Timing and control
TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .


Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC 0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

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INSTRUCTION CYCLE

In Basic Computer, a machine instruction is executed


in the following cycle:
Fetch an instruction from memory
Decode the instruction
Read the effective address from memory if the instruction has
an indirect address
Execute the instruction

After an instruction is executed, the cycle starts again


at step 1, for the next instruction
Note: Every different processor has its own (different)
instruction cycle

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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Instruction Cycle
FETCH and DECODE
Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15)

T1 S2

T0 S1 Bus

S0
Memory 7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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Instruction Cycle
DETERMINE THE TYPE OF INSTRUCTION
Start
SC

T0
AR PC
T1
IR M[AR], PC PC + 1
T2
Decode Opcode in IR(12-14),
AR IR(0-11), I IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)


D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)


I I

T3 T3 T3 T3
Execute Execute AR M[AR] Nothing
input-output register-reference
instruction instruction
SC 0 SC 0 Execute T4
memory-reference
instruction
SC 0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
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Instruction Cycle
REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction


Bi = IR(i) , i=0,1,2,...,11
r: SC 0
CLA rB11: AC 0
CLE rB10: E0
CMA rB9: AC AC
CME rB8: E E
CIR rB7: AC shr AC, AC(15) E, E AC(0)
CIL rB6: AC shl AC, AC(0) E, E AC(15)
INC rB5: AC AC + 1
SPA rB4: if (AC(15) = 0) then (PC PC+1)
SNA rB3: if (AC(15) = 1) then (PC PC+1)
SZA rB2: if (AC = 0) then (PC PC+1)
SZE rB1: if (E = 0) then (PC PC+1)
HLT rB0: S 0 (S is a start-stop flip-flop)
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MR Instructions
MEMORY REFERENCE INSTRUCTIONS
Operation
Symbol Symbolic Description
Decoder
AND D0 AC AC M[AR]
ADD D1 AC AC + M[AR], E Cout
LDA D2 AC M[AR]
STA D3 M[AR] AC
BUN D4 PC AR
BSA D5 M[AR] PC, PC AR + 1
ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4: DR M[AR] Read operand
D0T5: AC AC DR, SC 0 AND with AC
ADD to AC
D1T4: DR M[AR] Read operand
D1T5: AC AC + DR, E Cout, SC 0 Add to AC and store carry in E
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MEMORY REFERENCE INSTRUCTIONS
LDA: Load to AC
D2T4: DR M[AR]
D2T5: AC DR, SC 0
STA: Store AC
D3T4: M[AR] AC, SC 0
BUN: Branch Unconditionally
D4T4: PC AR, SC 0
BSA: Branch and Save Return Address
M[AR] PC, PC AR + 1
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135


Memory Memory
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MR Instructions
MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR] PC, AR AR + 1
D5T5: PC AR, SC 0

ISZ: Increment and Skip-if-Zero


D6T4: DR M[AR]
D6T5: DR DR + 1
D6T4: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0

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FLOWCHART FOR MEMORY REFERENCE
INSTRUCTIONS
Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR M[AR] DR M[AR] DR M[AR] M[AR] AC
SC 0

D0 T 5 D1 T 5 D2 T 5
AC AC DR AC AC + DR AC DR
SC 0 E Cout SC 0
SC 0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC AR M[AR] PC DR M[AR]
SC 0 AR AR + 1

D5 T 5 D6 T 5

PC AR DR DR + 1
SC 0
D6 T 6
M[AR] DR
If (DR = 0)
then (PC PC + 1)
SC 0

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer

Input-Output Configuration
Input-output Serial Computer
terminal communication registers and
interface
flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

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INPUT-OUTPUT AND INTERRUPT

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR

-The serial info. for the printer is stored in the OUTR

- INPR and OUTR communicate with the terminal


serially and with the AC in parallel.

- The flags are needed to synchronize the timing


difference between I/O device and the computer

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
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I/O and Interrupt
PROGRAM CONTROLLED DATA TRANSFER
-- CPU -- -- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop INPR new data, FGI 1
AC INPR, FGI 0

/* Output */ /* Initially FGO = 1 */ loop: If FGO = 1 goto loop


loop: If FGO = 0 goto loop consume OUTR, FGO 1
OUTR AC, FGO 0

FGI=0 FGO=1
Start Input Start Output

FGI 0
AC Data
yes yes
FGI=0
FGO=0
no
no
AC INPR
OUTR AC

yes More FGO 0


Character
yes More
no Character
END no
END
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INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, , 11

p: SC 0 Clear SC
INP pB11: AC(0-7) INPR, FGI 0 Input char. to AC
OUT pB10: OUTR AC(0-7), FGO 0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC PC + 1) Skip on output flag
ION pB7: IEN 1 Interrupt enable on
IOF pB6: IEN 0 Interrupt enable off

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I/O and Interrupt
PROGRAM-CONTROLLED INPUT/OUTPUT
Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
Input

LOOP, SKI DEV


BUN LOOP
INP DEV

Output

LOOP, LDA DATA


LOP, SKO DEV
BUN LOP
OUT DEV
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INTERRUPT INITIATED INPUT/OUTPUT
- Open communication only when some data has to be passed --> interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task


it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)


- can be set and cleared by instructions
- when cleared, the computer cannot be interrupted
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I/O and Interrupt
FLOWCHART FOR INTERRUPT CYCLE

R = Interrupt f/f

Instruction cycle=0 R =1 Interrupt cycle

Fetch and decode Store return address


instructions in location 0
M[0] PC

Execute IEN =0
instructions =1 Branch to location 1
PC 1
=1 FGI
=0
=1 FGO IEN 0
R0
=0
R1

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I/O and Interrupt
INTERRUPT CYCLE

- The interrupt cycle is a HW implementation of a branch


and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
-At memory address 1, the programmer must store a branch
instruction that sends the control to an interrupt service
routine
- The instruction that returns the control to the original
program is "indirect BUN 0"

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REGISTER TRANSFER OPERATIONS IN
INTERRUPT CYCLE
Memory
Before interrupt After interrupt cycle
0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0

Register Transfer Statements for Interrupt Cycle


- R F/F 1 if IEN (FGI + FGO)T0T1T2
T0T1T2 (IEN)(FGI + FGO): R 1

- The fetch and decode phases of the instruction cycle


must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR 0, TR PC
RT1: M[AR] TR, PC 0
RT2: PC PC + 1, IEN 0, R 0, SC 0
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I/O and Interrupt
FURTHER QUESTIONS ON INTERRUPT

How can the CPU recognize the device requesting an


interrupt ?

Since different devices are likely to require different


interrupt service routines, how can the CPU obtain the
starting address of the appropriate routine in each case ?

Should any device be allowed to interrupt the CPU while


another interrupt is being serviced ?

How can the situation be handled when two or more


interrupt requests occur simultaneously ?

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Description

COMPLETE COMPUTER DESCRIPTION


Flowchart
start
of Operations
SC 0, IEN 0, R 0

=0(Instruction =1(Interrupt
R
Cycle) Cycle)
RT0 RT0
AR PC AR 0, TR PC
RT1 RT1
IR M[AR], PC PC + 1 M[AR] TR, PC 0
RT2 RT2
AR IR(0~11), I IR(15) PC PC + 1, IEN 0
D0...D7 Decode IR(12 ~ 14) R 0, SC 0

=1(Register or I/O) D7 =0(Memory Ref)

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)


I I

D7IT3 D7IT3 D7IT3 D7IT3


Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7T4
Instruction

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Description
COMPLETE COMPUTER DESCRIPTION
MICROOPERATIONS`
Fetch RT0: AR PC
RT1: IR M[AR], PC PC + 1
Decode D0, ..., D7 Decode IR(12 ~ 14),
RT2:
AR IR(0 ~ 11), I IR(15)
Indirect
Interrupt D7IT3: AR M[AR]
T0T1T2(IEN)(FGI + FGO):
R1
AR 0, TR PC
RT0: M[AR] TR, PC 0
Memory-ReferenceRT1: PC PC + 1, IEN 0, R 0, SC 0
AND RT2:
ADD DR M[AR]
D0T4: AC AC DR, SC 0
LDA D0T5: DR M[AR]
D1T4: AC AC + DR, E Cout, SC 0
STA DR M[AR]
BUN D1T5:
D2T4: AC DR, SC 0
BSA
M[AR] AC, SC 0
D2T5:
ISZ PC AR, SC 0
D3T4: M[AR] PC, AR AR + 1
D4T4: PC AR, SC 0
D5T4: DR M[AR]
D5T5: DR DR + 1
D6T4: M[AR] DR, if(DR=0) then (PC PC + 1),
D6T5Applications
: SC 0
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49
Description
COMPLETE COMPUTER DESCRIPTION
MICROOPERATIONS
Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC 0
CLA AC 0
CLE rB11: E0
CMA rB10: AC AC
CME rB9: E E
CIR AC shr AC, AC(15) E, E AC(0)
CIL rB8:
AC shl AC, AC(0) E, E AC(15)
INC rB7: AC AC + 1
SPA rB6: If(AC(15) =0) then (PC PC + 1)
SNA If(AC(15) =1) then (PC PC + 1)
SZA rB5:
If(AC = 0) then (PC PC + 1)
SZE rB4: If(E=0) then (PC PC + 1)
HLT rB3: S0
Input-Output
rB2:
(Common to all input-output instructions)
rB1: (i = 6,7,8,9,10,11)
rB0: SC 0
INP AC(0-7) INPR, FGI 0
OUT OUTR AC(0-7), FGO 0
SKI
D7IT3 = p
If(FGI=1) then (PC PC + 1)
SKO IR(i) = Bi If(FGO=1) then (PC PC + 1)
ION p: IEN 1
IOF pB11: IEN 0
pB10:
pB9:
pB8: U1.
Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania
50
DESIGN OF BASIC COMPUTER(BC)
Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC
Control Logic Gates
- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit
Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
51
Design of Basic Computer
CONTROL OF REGISTERS AND MEMORY
Address Register; AR
Scan all of the register transfer statements that change the content of AR:
RT0: AR PC LD(AR)
RT2: AR IR(0-11) LD(AR)
D7IT3: AR M[AR] LD(AR)
RT0: AR 0 CLR(AR)
D5T4: AR AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D'7IT3


CLR(AR) = RT0
INR(AR) = D5T4
12 12
From bus AR To bus
D'7
I
LD Clock
T3
T2 INR
CLR
R
T0
D
T4

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
52
Design of Basic Computer
CONTROL OF FLAGS
IEN: Interrupt Enable Flag
pB7: IEN 1 (I/O Instruction)
pB6: IEN 0 (I/O Instruction)
RT2: IEN 0 (Interrupt)

p = D7IT3 (Input/Output Instruction)

D
7
p
I J IEN
Q
B7
T3

B6
K
R
T2

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53
CONTROL OF COMMON BUS
Design of Basic Computer

x1
x2 S2
Multiplexer
x3
Encoder S1 bus select
x4
x5 inputs
x6 S0
x7

selected
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

For AR D4T4: PC AR
D5T5: PC AR

x1 = D4T4 + D5T5

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54
DESIGN OF ACCUMULATOR LOGIC
Circuits associated with AC 16
Adder and
16 16 16
From DR logic AC

8 circuit To bus
From INPR

LD INR CLR Clock

Control
gates

All the statements that change the content of AC


D0T5: AC AC DR AND with DR
D1T5: AC AC + DR Add with DR
D2T5: AC DR Transfer from DR
pB11: AC(0-7) INPR Transfer from INPR
rB9: AC AC Complement
rB7 : AC shr AC, AC(15) E Shift right
rB6 : AC shl AC, AC(0) E Shift left
rB11 : AC 0 Clear
rB5 : AC AC + 1 Increment
Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
55
CONTROL OF AC REGISTER

Gate structures for controlling


the LD, INR, and CLR of AC

From Adder 16 16 To bus


and Logic AC
D0 AND LD Clock
T5 INR
D1 ADD CLR

D2 DR
T5
p INPR
B11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B11
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56
ALU (ADDER AND LOGIC CIRCUIT)

One stage of Adder and Logic circuit


DR(i)
AC(i)

AND

Ci ADD LD
FA Ii J Q
DR AC(i)
C i+1

INPR K
From
INPR
bit(i)
COM

SHR
AC(i+1)
SHL
AC(i-1)

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57
CONCLUSIONS

Designing of the instructions format


Types of Computer cycles
Design of Control Logic

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58
SUMMARY
Computers structure indicates its internal connections
Functional structure identifies functional block and relationship
between these blocks
Physical structure identifies the physical modules and
interconnection between them.
Computer function indicates the behavior. At overall level its
function is program execution.
Relation between computer organization and architecture.
Design of ALU
Design of bus, its interconnection and control logic

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59
CONTROL UNIT DESIGN

U1.
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60
LEARNING OBJECTIVES

Microprogammed Control Unit


Control Unit Design
Introduction to Pipelining

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61
MICROPROGRAMMED CONTROL

Control Memory

Sequencing Microinstructions

Microprogram Example

Design of Control Unit

Microinstruction Format

Nanostorage and Nanoprogram

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62
COMPARISON OF CONTROL UNIT
IMPLEMENTATIONS
Control Unit Implementation
Combinational Logic Circuits (Hard-wired)
Control Data
Memory IR Status F/Fs

Control Unit's State


Timing State
Combinational Control CPU
Logic Circuits Points
Ins. Cycle State

Microprogram

M Control Data
e
m
o IR Status F/Fs
r
y

C Control C
Next Address Storage C
S S D P CPU
Generation A (-program D
Logic s
R memory) R }

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63
TERMINOLOGY
Microprogram
- Program stored in memory that generates all the
control signals required to execute the instruction set
correctly
- Consists of microinstructions

Microinstruction
- Contains a control word and a sequencing word
Control Word - All the control information required for one
clock cycle
Sequencing Word - Information needed to decide the
next microinstruction address
- Vocabulary to write a microprogram

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64
Cont.

Control Memory(Control Storage: CS)


- Storage in the microprogrammed control unit to store the
microprogram
Writeable Control Memory(Writeable Control Storage:WCS)
- CS whose contents can be modified
-> Allows the microprogram can be changed
-> Instruction set can be changed or modified
Dynamic Microprogramming
- Computer system whose control unit is implemented with
a microprogram in WCS
- Microprogram can be changed by a systems programmer
or a user

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65
Cont

Sequencer (Microprogram Sequencer)


A Microprogram Control Unit that determines
the Microinstruction Address to be executed
in the next clock cycle

- In-line Sequencing
- Branch
- Conditional Branch
- Subroutine
- Loop
- Instruction OP-code mapping

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66
MICROINSTRUCTION SEQUENCING

Instruction code

Mapping
logic

Status Branch MUX Multiplexers


bits logic select
Subroutine
Control address register register
(CAR) (SBR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

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67
MICROINSTRUCTION SEQUENCING

Sequencing Capabilities Required in a Control Storage

- Incrementing of the control address register


- Unconditional and conditional branches
- A mapping process from the bits of the machine
instruction to an address for control memory
- A facility for subroutine call and return

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Sequencing
CONDITIONAL BRANCH
Load address
Control address register

Increment

MUX
Control memory

...
Status bits
(condition)

Condition select Micro-operations

Next address

Conditional Branch
If Condition is true, then Branch (address from
the next address field of the current microinstruction)
else Fall Through
Conditions to Test: O(overflow), N(negative),
Z(zero), C(carry), etc.
Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1
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Sequencing

MAPPING OF INSTRUCTIONS
Direct Mapping Address
OP-codes of Instructions 0000 ADD Routine
0001 AND Routine
ADD 0000 0010 LDA Routine
AND 0001 . 0011 STA Routine
LDA 0010 . 0100 BUN Routine
.
STA 0011
Control
BUN 0100 Storage

Mapping
10 xxxx 010
Bits Address
10 0000 010 ADD Routine

10 0001 010 AND Routine

10 0010 010 LDA Routine

10 0011 010 STA Routine

10 0100 010 BUN Routine

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MAPPING OF INSTRUCTIONS TO
MICROROUTINES
Mapping from the OP-code of an instruction to the
address of the Microinstruction which is the starting
microinstruction of its execution microprogram

Machine OP-code
Instruction 1 0 1 1 Address

Mapping bits 0 x x x x 0 0
Microinstruction
address 0 1 0 1 1 0 0

Mapping function implemented by ROM or PLA


OP-code

Mapping memory
(ROM or PLA)

Control address register

Control Memory
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Microprogram
MICROPROGRAM EXAMPLE
Computer Configuration

MUX
10 0
AR
Address Memory
10 0 2048 x 16
PC

MUX

15 0
6 0 6 0 DR
SBR CAR

Control memory Arithmetic


128 x 20 logic and
shift unit
Control unit
15 0
AC

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MACHINE INSTRUCTION FORMAT

Machine instruction format


15 14 11 10 0
I Opcode Address

Sample machine instructions


Symbol OP-code Description
EA is the effective address
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC EA)
STORE 0010 M[EA] AC
EXCHANGE 0011 AC M[EA], M[EA] AC

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields


CD: Condition for branching
BR: Branch field
AD: Address field

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MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3

F1 Microoperation Symbol F2 Microoperation Symbol


000 None NOP 000 None NOP
001 AC AC + DR ADD 001 AC AC - DR SUB
010 AC 0 CLRAC 010 AC AC DR OR
011 AC AC + 1 INCAC 011 AC AC DR AND
100 AC DR DRTAC 100 DR M[AR] READ
101 AR DR(0-10) DRTAR 101 DR AC ACTDR
110 AR PC PCTAR 110 DR DR + 1 INCDR
111 M[AR] DR WRITE 111 DR(0-10) PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC AC DR XOR
010 AC AC COM
011 AC shl AC SHL
100 AC shr AC SHR
101 PC PC + 1 INCPC
110 PC AR ARTPC
111 Reserved

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MICROINSTRUCTION FIELD DESCRIPTIONS -
CD, BR

CD Condition Symbol Comments


00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR AD if condition = 1
CAR CAR + 1 if condition = 0
01 CALL CAR AD, SBR CAR + 1 if condition = 1
CAR CAR + 1 if condition = 0
10 RET CAR SBR (Return from subroutine)
11 MAP CAR(2-5) DR(11-14), CAR(0,1,6) 0

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Microprogram
SYMBOLIC MICROINSTRUCTIONS
Symbols are used in microinstructions as in assembly language
A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler.

Sample Format
five fields: label; micro-ops; CD; BR; AD

Label: may be empty or may specify a symbolic


address terminated with a colon

Micro-ops: consists of one, two, or three symbols


separated by commas

CD: one of {U, I, S, Z}, where U: Unconditional Branch


I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}


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SYMBOLIC MICROPROGRAM
- FETCH ROUTINE -
During FETCH, Read an instruction from memory
and decode the instruction and update PC

Sequence of microoperations in the fetch cycle:


AR PC
DR M[AR], PC PC + 1
AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0

Symbolic microprogram for the fetch cycle:


ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

Binary equivalents translated by an assembler


Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000

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SYMBOLIC MICROPROGRAM
Control Storage: 128 20-bit words
The first 64 words: Routines for the 16 machine instructions
The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

Partial Symbolic Microprogram


Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH

ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH

ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH

ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET

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Microprogram
BINARY MICROPROGRAM
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000

BRANCH 4 0000100 000 000 000 10 00 0000110


5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001


65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000

This microprogram can be implemented using ROM

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DESIGN OF CONTROL UNIT
- DECODING ALU CONTROL INFORMATION -

microoperation fields
F1 F2 F3

3 x 8 decoder 3 x 8 decoder 3 x 8 decoder


76 54 3 21 0 7 6 54 3 21 0 76 54 3 21 0

AND
ADD AC
Arithmetic
logic and DR
DRTAC shift unit
PCTAR

DRTAR

From From
PC DR(0-10) Load
AC

Select 0 1
Multiplexers

Load Clock
AR

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MICROPROGRAM SEQUENCER
- NEXT MICROINSTRUCTION ADDRESS LOGIC -
Branch, CALL Address
External RETURN form Subroutine
(MAP)
In-Line
S1S0 Address Source
00 CAR + 1, In-Line 3 2 1 0
S1 MUX1 L
01 SBR RETURN SBR Subroutine
S0 CALL
10 CS(AD), Branch or CALL Address
11 MAP source
selection Incrementer

Clock CAR

Control Storage

MUX-1 selects an address from one of four sources and routes it into a CAR

- In-Line Sequencing CAR + 1


- Branch, Subroutine Call CS(AD)
- Return from Subroutine Output of SBR
- New Machine instruction MAP
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MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -

1 L L(load SBR with PC)


From I MUX2 Test
CPU SZ T for subroutine Call
Input
Select BR field I0 logic S0 for next address
of CS I1
S1 selection
CD Field of CS

Input Logic
I0I1T Meaning Source of Address S 1S0 L

000 In-Line CAR+1 00 0


001 JMP CS(AD) 10 0
010 In-Line CAR+1 00 0
011 CALL CS(AD) and SBR <- CAR+1 10 1
10x RET SBR 01 0
11x MAP DR(11-14) 11 0

S0 = I 0
S1 = I0I1 + I0T
L = I0I1T
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MICROPROGRAM SEQUENCER
External
(MAP)

L
I0 3 2 1 0
Input Load
I1 S1 MUX1 SBR
logic
T S0

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...

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MICROINSTRUCTION FORMAT

Information in a Microinstruction
- Control Information
- Sequencing Information
- Constant
Information which is useful when feeding into the system

These information needs to be organized in some way for


- Efficient use of the microinstruction bits
- Fast decoding

Field Encoding

- Encoding the microinstruction bits


- Encoding slows down the execution speed
due to the decoding delay
- Encoding also reduces the flexibility due to
the decoding hardware

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HORIZONTAL AND VERTICAL
MICROINSTRUCTION FORMAT
Horizontal Microinstructions
Each bit directly controls each micro-operation or each control point
Horizontal implies a long microinstruction word
Advantages: Can control a variety of components operating in parallel.
--> Advantage of efficient hardware utilization
Disadvantages: Control word bits are not fully utilized
--> CS becomes large --> Costly
Vertical Microinstructions
A microinstruction format that is not horizontal
Vertical implies a short microinstruction word
Encoded Microinstruction fields
--> Needs decoding circuits for one or two levels of decoding

One-level decoding Two-level decoding

Field A Field B
Field A Field B
2 bits 6 bits
2 bits 3 bits

2x4 6 x 64
2x4 3x8 Decoder Decoder
Decoder Decoder

Decoder and
1 of 4 1 of 8 selection logic

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NANOSTORAGE Control Storage
Hierarchy

AND NANOINSTRUCTION
The decoder circuits in a vertical microprogram
storage organization can be replaced by a ROM
=> Two levels of control storage
First level - Control Storage
Second level - Nano Storage

Two-level microprogram

First level
-Vertical format Microprogram
Second level
-Horizontal format Nanoprogram
- Interprets the microinstruction fields, thus converts a vertical
microinstruction format into a horizontal
nanoinstruction format.

Usually, the microprogram consists of a large number of short


microinstructions, while the nanoprogram contains fewer words
with longer nanoinstructions.

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TWO-LEVEL MICROPROGRAMMING
EXAMPLE Control Storage Hierarchy
* Microprogram: 2048 microinstructions of 200 bits each
* With 1-Level Control Storage: 2048 x 200 = 409,600 bits
* Assumption:
256 distinct microinstructions among 2048
* With 2-Level Control Storage:
Nano Storage: 256 x 200 bits to store 256 distinct nanoinstructions
Control storage: 2048 x 8 bits
To address 256 nano storage locations 8 bits are needed
* Total 1-Level control storage: 409,600 bits
Total 2-Level control storage: 67,584 bits (256 x 200 + 2048 x 8)

Control address register

11 bits

Control memory
2048 x 8

Microinstruction (8 bits)
Nanomemory address

Nanomemory
256 x 200

Nanoinstructions (200 bits)

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CONCLUSIONS

Micro programmed control organization


Address Sequencing
Mapping of instruction
Design of micro instructions
Symbolic/Binary Micro program
Design of control unit

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CENTRAL PROCESSING UNIT

Introduction

General Register Organization

Stack Organization

Instruction Formats

Addressing Modes

Data Transfer and Manipulation

Program Control

Reduced Instruction Set Computer

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Introduction
MAJOR COMPONENTS OF CPU
Storage Components
Registers
Flags

Execution (Processing) Components


Arithmetic Logic Unit(ALU)
Arithmetic calculations, Logical computations, Shifts/Rotates

Transfer Components
Bus

Control Components
Control Unit Register
File ALU

Control Unit

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REGISTERS
In Basic Computer, there is only one general purpose register, the
Accumulator (AC)
In modern CPUs, there are many general purpose registers
It is advantageous to have many registers
Transfer between registers within the processor are relatively fast
Going off the processor to access memory is much slower

How many registers will be the best ?

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GENERAL REGISTER ORGANIZATION

Clock Input

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
3x8 A bus B bus
decoder

SELD
OPR ALU

Output

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OPERATION OF CONTROL UNIT
The control unit
Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 R2 + R3
[1] MUX A selector (SELA): BUS A R2
[2] MUX B selector (SELB): BUS B R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1 Out Bus
3 3 3 5

Control Word SELA SELB SELD OPR

Encoding of register selection fields Binary


Code SELA SELB
SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7
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93
Control

ALU CONTROL
Encoding of ALU operations

OPR
Select Operation Symbol

00000 TransferA TSFA


00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

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Control

ALU CONTROL

Examples of ALU Microoperations

Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1 R2 R3 R2 R3 R1 SUB 010 011 001 00101
R4 R4 R5 R4 R5 R4 OR 100 101 100 01010
R6 R6 + 1 R6 - R6 INCA 110 000 110 00001
R7 R1 R1 - R7 TSFA 001 000 111 00000
Output R2 R2 - None TSFA 010 000 000 00000
Output Input Input - None TSFA 000 000 000 00000
R4 shl R4 R4 - R4 SHLA 100 000 100 11000
R5 0 R5 R5 R5 XOR 101 101 101 01100

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Stack Organization

REGISTER STACK ORGANIZATION


Stack
- Very useful feature for nested subroutines, nested interrupt services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP
- Only PUSH and POP operations are applicable
stack Address

Register Stack 63
Flags
FULL EMPTY

Stack pointer 4
SP C 3
6 bits B 2
A 1
Push, Pop operations 0
DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */

PUSH POP
SP SP + 1 DR M[SP]
M[SP] DR SP SP 1
If (SP = 0) then (FULL 1) If (SP = 0) then (EMPTY 1)
EMPTY 0 FULL 0
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MEMORY STACK ORGANIZATION
1000
Program
Memory with Program, Data, PC (instructions)
and Stack Segments
Data
AR (operands)

SP 3000
stack
3997
3998
3999
4000
4001
- A portion of memory is used as a stack with a Stack grows
processor register as a stack pointer In this direction

- PUSH: SP SP - 1
M[SP] DR
- POP: DR M[SP]
SP SP + 1
- Most computers do not provide hardware to check stack overflow (full

stack) or underflow (empty stack) must be done in software


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Stack Organization

REVERSE POLISH NOTATION


Arithmetic Expressions: A + B
A+ B Infix notation
+ AB Prefix or Polish notation
AB + Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack
manipulation

Evaluation of Arithmetic Expressions


Any arithmetic expression can be expressed in parenthesis-free
Polish notation, including reverse Polish notation

(3 * 4) + (5 * 6) 34*56*+

6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +

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PROCESSOR ORGANIZATION
In general, most processors are organized in one of 3 ways
Single register (Accumulator) organization
Basic Computer is a good example
Accumulator is the only general purpose register
General register organization
Used by most modern computer processors
Any of the registers can be used as the source or destination for
computer operations
Stack organization
All operations are done using the hardware stack
For example, an OR instruction will pop the two top
elements from the stack, do a logical OR on them, and
push the result on the stack

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INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor register(s)
Mode field - determines how the address field is to be interpreted (to
get effective address or the operand)

The number of address fields in the instruction format


depends on the internal organization of CPU

The three most common CPU organizations:


Single accumulator organization:
ADD X /* AC AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1 R2 + R3 */
ADD R1, R2 /* R1 R1 + R2 */
MOV R1, R2 /* R1 R2 */
ADD R1, X /* R1 R1 + M[X] */
Stack organization:
PUSH X /* TOS M[X] */
ADD
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Instruction Format
THREE AND TWO-ADDRESS INSTRUCTIONS

Three-Address Instructions

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1 M[A] + M[B] */
ADD R2, C, D /* R2 M[C] + M[D] */
MUL X, R1, R2 /* M[X] R1 * R2 */

- Results in short programs


- Instruction becomes long (many bits)

Two-Address Instructions

Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1 M[A] */


ADD R1, B /* R1 R1 + M[A] */
MOV R2, C /* R2 M[C] */
ADD R2, D /* R2 R2 + M[D] */
MUL R1, R2 /* R1 R1 * R2 */
MOV X, R1 /* M[X] R1 */

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Instruction Format
ONE AND ZERO-ADDRESS INSTRUCTIONS
One-Address Instructions
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC M[A] */
ADD B /* AC AC + M[B] */
STORE T /* M[T] AC */
LOAD C /* AC M[C] */
ADD D /* AC AC + M[D] */
MUL T /* AC AC * M[T] */
STORE X /* M[X] AC */
Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :

PUSH A /* TOS A */
PUSH B /* TOS B */
ADD /* TOS (A + B) */
PUSH C /* TOS C */
PUSH D /* TOS D */
ADD /* TOS (C + D) */
MUL /* TOS (C + D) * (A + B) */
POP X /* M[X] TOS */ U1.
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ADDRESSING MODES

Addressing Modes

* Specifies a rule for interpreting or modifying the


address field of the instruction (before the operand
is actually referenced)

* Variety of addressing modes

- to give programming flexibility to the user


- to use the bits in the address field of the instruction
efficiently

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TYPES OF ADDRESSING MODES

Implied Mode
Address of the operands are specified implicitly
in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack [SP]
- Examples from Basic Computer
CLA, CME, INP

Immediate Mode
Instead of specifying the address of the operand,
operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand

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TYPES OF ADDRESSING MODES

Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)

Register Indirect Mode


Instruction specifies a register which contains
the memory address of the operand
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)

Autoincrement or Autodecrement Mode


- When the address in the register is used to access memory, the
value in the register is incremented or decremented by 1
automatically
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TYPES OF ADDRESSING MODES

Direct Address Mode


Instruction specifies the memory address which
can be used directly to access the memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address
for a large physical memory space
- EA = IR(addr) (IR(addr): address field of IR)

Indirect Addressing Mode


The address field of an instruction specifies the address of a memory
location that contains the address of the operand
- When the abbreviated address is used large physical memory can be
addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]

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106
TYPES OF ADDRESSING MODES

Relative Addressing Modes


The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a designated
register to calculate the address of the operand
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of
address bits
- EA = f(IR(address), R), R is sometimes implied
3 different Relative Addressing Modes depending on R;
* PC Relative Addressing Mode (R = PC)
- EA = PC + IR(address)
* Indexed Addressing Mode (R = IX, where IX: Index Register)
- EA = IX + IR(address)
* Base Register Addressing Mode
(R = BAR, where BAR: Base Address Register)
- EA = BAR + IR(address)

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ADDRESSING MODES
- EXAMPLES -
Address Memory
200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction
R1 = 400

399 450
XR = 100
400 700

AC
500 800

600 900

Addressing Effective Content 702 325


Mode Address of AC
Direct address 500 /* AC (500) */ 800
Immediate operand - /* AC 500 */ 500 800 300
Indirect address 800 /* AC ((500)) */ 300
Relative address 702 /* AC (PC+500) */ 325
Indexed address 600 /* AC (RX+500) */ 900
Register - /* AC R1 */ 400
Register indirect 400 /* AC (R1) */ 700
Autoincrement 400 /* AC (R1)+ */ 700
Autodecrement 399 /* AC -(R) */ 450
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DATA TRANSFER INSTRUCTIONS
Typical Data Transfer Instructions
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Data Transfer Instructions with Different Addressing Modes
Mode Assembly Register Transfer
Convention
Direct address LD ADR AC M[ADR]
Indirect address LD @ADR AC M[M[ADR]]
Relative address LD $ADR AC M[PC + ADR]
Immediate operand LD #NBR AC NBR
Index addressing LD ADR(X) AC M[ADR + XR]
Register LD R1 AC R1
Register indirect LD (R1) AC M[R1]
Autoincrement LD (R1)+ AC M[R1], R1 R1 + 1
Autodecrement LD -(R1) R1 R1 - 1, AC M[R1]
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DATA MANIPULATION INSTRUCTIONS
Three Basic Types: Arithmetic instructions
Logical and bit manipulation instructions
Shift instructions
Arithmetic Instructions
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2s Complement) NEG

Logical and Bit Manipulation Instructions Shift Instructions


Name Mnemonic Name Mnemonic
Clear CLR Logical shift right SHR
Complement COM Logical shift left SHL
AND AND Arithmetic shift right SHRA
OR OR Arithmetic shift left SHLA
Exclusive-OR XOR Rotate right ROR
Clear carry CLRC Rotate left ROL
Set carry SETC Rotate right thru carry RORC
Complement carry COMC Rotate left thru carry ROLC
Enable interrupt EI
Disable interrupt DI
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FLAG, PROCESSOR STATUS WORD
In Basic Computer, the processor had several (status) flags 1 bit
value that indicated various information about the processors state
E, FGI, FGO, I, IEN, R
In some processors, flags like these are often combined into a register
the processor status register (PSR); sometimes called a processor
status word (PSW)
Common flags in PSW are
C (Carry): Set to 1 if the carry out of the ALU is 1
S (Sign): The MSB bit of the ALUs output Status Flag Circuit
Z (Zero): Set to 1 if the ALUs output is all 0s
A B
V (Overflow): Set to 1 if there is an overflow 8 8
c7
c8 8-bit ALU
F7 - F0
V Z S C
F7
Check for 8
zero output
F
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PROGRAM CONTROL INSTRUCTIONS
+1
In-Line Sequencing (Next instruction is fetched
from the next adjacent location in the memory)
PC
Address from other source; Current Instruction,
Stack, etc; Branch, Conditional Branch,
Subroutine, etc

Program Control Instructions


Name Mnemonic
Branch BR
Jump JMP
Skip SKP CMP and TST instructions do not
Call CALL retain their results of operations
( and AND, respectively).
Return RTN They only set or clear certain
Compare(by ) CMP Flags.
Test(by AND) TST

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Program Control
CONDITIONAL BRANCH INSTRUCTIONS

Mnemonic Branch condition Tested condition


BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
Unsigned compare conditions (A - B)
BHI Branch if higher A>B
BHE Branch if higher or equal A B
BLO Branch if lower A<B
BLOE Branch if lower or equal A B
BE Branch if equal A=B
BNE Branch if not equal A B
Signed compare conditions (A - B)
BGT Branch if greater than A>B
BGE Branch if greater or equal A B
BLT Branch if less than A<B
BLE Branch if less or equal A B
BE Branch if equal A=B
BNE Branch if not equal A B

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Program Control
SUBROUTINE CALL AND RETURN
Subroutine Call Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save return address

Two Most Important Operations are Implied;

* Branch to the beginning of the Subroutine


- Same as the Branch or Conditional Branch

* Save the Return Address to get the address


of the location in the Calling Program upon
exit from the Subroutine
CALL
Locations for storing Return Address SP SP - 1
Fixed Location in the subroutine (Memory) M[SP] PC
Fixed Location in memory PC EA
In a processor Register
In memory stack RTN
- most efficient way PC M[SP]
SP SP + 1

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Program Control`
PROGRAM INTERRUPT
Types of Interrupts
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device Data transfer request or Data transfer complete
- Timing Device Timeout
- Power Failure
- Operator

Internal interrupts (traps)


Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation

Software Interrupts
Both External and Internal Interrupts are initiated by the computer HW.
Software Interrupts are initiated by the executing an instruction.
- Supervisor Call Switching from a user mode to the supervisor mode
Allows to execute a certain class of operations
which are
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Dr. Deepali Kamthania U1.
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Program Control
INTERRUPT PROCEDURE
Interrupt Procedure and Subroutine Call
The interrupt is usually initiated by an internal or an external signal
rather than from the execution of an instruction (except for the
software interrupt)
The address of the interrupt service program is determined by the
hardware rather than from the address field of an instruction
An interrupt procedure usually stores all the information necessary
to define the state of CPU rather than storing only the PC.
The state of the CPU is determined from;
Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state depending on the CPU
architectures

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116
RISC: HISTORICAL BACKGROUND
IBM System/360, 1964
The real beginning of modern computer architecture
Distinction between Architecture and Implementation
Architecture: The abstract structure of a computer
seen by an assembly-language programmer
Hardware
-program
Compiler
High-Level Instruction
Language Hardware
Set
Architecture
Hardware

Implementation

Continuing growth in semiconductor memory and microprogramming


A much richer and complicated instruction sets
CISC(Complex Instruction Set Computer)

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ARGUMENTS ADVANCED AT THAT TIME

Richer instruction sets would simplify compilers


Richer instruction sets would alleviate the software
crisis
move as much functions to the hardware as possible

Richer instruction sets would improve architecture


quality

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ARCHITECTURE DESIGN PRINCIPLES
- IN 70s - RISC

Large microprograms would add little or nothing


to the cost of the machine
Rapid growth of memory technology
Large General Purpose Instruction Set

Microprogram is much faster than the machine instructions


Microprogram memory is much faster than main memory
Moving the software functions into
microprogram for the high performance machines

Execution speed is proportional to the program size


Architectural techniques that led to small program
High performance instruction set

Number of registers in CPU has limitations


Very costly
Difficult to utilize them efficiently

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COMPARISONS OF EXECUTION
MODELS RISC

AB+C Data: 32-bit

Register-to-register
8 4 16
Load rB B
Load rC C
Add rA rB rC
Store rA A

I = 104b; D = 96b; M = 200b

Memory-to-register
8 16
Load B
Add C
Store A

I = 72b; D = 96b; M = 168b


Memory-to-memory
8 16 16 16
Add B C A
I = 56b; D = 96b; M = 152b
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FOUR MODERN ARCHITECTURES RISC

IN 70s

DEC Xerox Intel


IBM 370/168 VAX-11/780 Dorado iAPX-432
Year 1973 1978 1978 1982
# of instrs. 208 303 270 222
Control mem. size 420 Kb 480 Kb 136 Kb 420 Kb
Instr. size (bits) 16-48 16-456 8-24 6-321
Technology ECL MSI TTL MSI ECL MSI NMOS VLSI
Execution model reg-mem reg-mem stack stack
mem-mem mem-mem mem-mem
reg-reg reg-reg
Cache size 64 Kb 64 Kb 64 Kb 64 Kb

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COMPLEX INSTRUCTION SET
COMPUTER
These computers with many instructions and
addressing modes came to be known as
Complex Instruction Set Computers (CISC)

One goal for CISC machines was to have a


machine language instruction to match each
high-level language statement type

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VARIABLE LENGTH INSTRUCTIONS
The large number of instructions and addressing modes led CISC
machines to have variable length instruction formats
The large number of instructions means a greater number of bits to
specify them
In order to manage this large number of opcodes efficiently, they were
encoded with different lengths:
More frequently used instructions were encoded using short opcodes.
Less frequently used ones were assigned longer opcodes.
Also, multiple operand instructions could specify different addressing
modes for each operand
For example,
Operand 1 could be a directly addressed register,
Operand 2 could be an indirectly addressed memory location,
Operand 3 (the destination) could be an indirectly addressed register.
All of this led to the need to have different length instructions in different
situations, depending on the opcode and operands used

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Cont
For example, an instruction that only specifies register operands
may only be two bytes in length
One byte to specify the instruction and addressing mode
One byte to specify the source and destination registers.

An instruction that specifies memory addresses for operands may


need five bytes
One byte to specify the instruction and addressing mode
Two bytes to specify each memory address
Maybe more if theres a large amount of memory.

Variable length instructions greatly complicate the fetch and decode


problem for a processor

The circuitry to recognize the various instructions and to properly


fetch the required number of bytes for operands is very complex

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COMPLEX INSTRUCTION SET
COMPUTER
Another characteristic of CISC computers is that they have instructions
that act directly on memory addresses
For example,
ADD L1, L2, L3
that takes the contents of M[L1] adds it to the contents of M[L2] and stores the result
in location M[L3]
An instruction like this takes three memory access cycles to execute
That makes for a potentially very long instruction execution cycle

The problems with CISC computers are

The complexity of the design may slow down the processor,


The complexity of the design may result in costly errors in the processor design and
implementation,
Many of the instructions and addressing modes are used rarely, if ever

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125
SUMMARY: CRITICISMS ON CISC
High Performance General Purpose Instructions

- Complex Instruction
Format, Length, Addressing Modes
Complicated instruction cycle control due to the complex
decoding HW and decoding process

- Multiple memory cycle instructions


Operations on memory data
Multiple memory accesses/instruction

- Microprogrammed control is necessity


Microprogram control storage takes substantial portion of CPU
chip area
Semantic Gap is large between machine instruction and
microinstruction

- General purpose instruction set includes all the features


required by individually different applications
When any one application is running, all the features required by
the other applications are extra burden to the application
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126
REDUCED INSTRUCTION SET
COMPUTERS
In the late 70s and early 80s there was a reaction to the
shortcomings of the CISC style of processors
Reduced Instruction Set Computers (RISC) were proposed as
an alternative
The underlying idea behind RISC processors is to simplify the
instruction set and reduce instruction execution time

RISC processors often feature:

Few instructions
Few addressing modes
Only load and store instructions access memory
All other operations are done using on-processor registers
Fixed length instructions
Single cycle execution of instructions
The control unit is hardwired, not microprogrammed.

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Cont
Since all but the load and store instructions use only registers for
operands, only a few addressing modes are needed
By having all instructions the same length, reading them in is easy and
fast
The fetch and decode stages are simple, looking much more like
Manos Basic Computer than a CISC machine
The instruction and address formats are designed to be easy to
decode
Unlike the variable length CISC instructions, the opcode and register
fields of RISC instructions can be decoded simultaneously
The control logic of a RISC processor is designed to be simple and
fast
The control logic is simple because of the small number of instructions
and the simple addressing modes
The control logic is hardwired, rather than microprogrammed, because
hardwired control is faster
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RISC

ARCHITECTURAL METRIC
A B + C
B A+ C
DD -B
Register-to-register (Reuse of operands)
8 4 16
Load rB B
Load rC C
Add rA rB rC I = 228b
Store rA A
Add rB rA rC D = 192b
Store rB B M = 420b
Load rD D
Sub rD rD rB
Store rD D

Register-to-register (Compiler allocates operands in registers)


8 4 4 4
Add rA rB rC I = 60b
Add rB rA rC D = 0b
Sub rD rD rB M = 60b
Memory-to-memory
8 16 16 16
Add B C A I = 168b
Add A C B D = 288b
Sub B D D M = 456b
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CHARACTERISTICS OF INITIAL RISC
MACHINES

IBM 801 RISC I MIPS


Year 1980 1982 1983
Number of
instructions 120 39 55
Control memory
size 0 0 0
Instruction
size (bits) 32 32 32
Technology ECL MSI NMOS VLSI NMOS VLSI
Execution model reg-reg reg-reg reg-reg

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COMPARISON OF INSTRUCTION
SEQUENCE 32b memory port
RISC

A B+C OP DEST SOUR1 SOUR2


register
A A+1 RISC 1 ADD rA rB
operand
rC

DD-B ADD rA rA
immediate
operand
1

register
SUB rD rD rB
operand

VAX ADD
(3 operands)
register
operand
B register
operand
C register
operand
A

INC register SUB register


A B
(1 operands) operand (2 operands) operand
register D
operand

432 3 operands
B C ...
in memory
A
... C A D
D
A 1 operand I
D A N
D in memory C
I 2 operands
N B
in memory D ...
C
... D SUB

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131
REGISTERS

By simplifying the instructions and addressing modes,


there is space available on the chip or board of a RISC
CPU for more circuits than with a CISC processor
This extra capacity is used to
Pipeline instruction execution to speed up instruction
execution
Add a large number of registers to the CPU

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PIPELINING

A very important feature of many RISC processors is the


ability to execute an instruction each clock cycle
This may seem nonsensical, since it takes at least once
clock cycle each to fetch, decode and execute an
instruction.
It is however possible, because of a technique known as
pipelining
Well study this in detail later
Pipelining is the use of the processor to work on different
phases of multiple instructions in parallel

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Cont
For instance, at one time, a pipelined processor may be
Executing instruction it
Decoding instruction it+1
Fetching instruction it+2 from memory

So, if were running three instructions at once, and it takes an


average instruction three cycles to run, the CPU is executing an
average of an instruction a clock cycle

As well see when we cover it in depth, there are complications


For example, what happens to the pipeline when the processor branches

However, pipelined execution is an integral part of all modern


processors, and plays an important role

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REGISTERS

By having a large number of general purpose registers, a processor


can minimize the number of times it needs to access memory to load
or store a value
This results in a significant speed up, since memory accesses are
much slower than register accesses
Register accesses are fast, since they just use the bus on the CPU
itself, and any transfer can be done in one clock cycle
To go off-processor to memory requires using the much slower
memory (or system) bus
It may take many clock cycles to read or write to memory across the
memory bus
The memory bus hardware is usually slower than the processor
There may even be competition for access to the memory bus by other devices in
the computer (e.g. disk drives)
So, for this reason alone, a RISC processor may have an advantage
over a comparable CISC processor, since it only needs to access
memory
for its instructions, and
occasionally to load or store a memory value

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UTILIZING RISC REGISTERS
-REGISTER WINDOW-

<Weighted Relative Dynamic Frequency of HLL Operations>

Machine- Memory
Dynamic Instruction Reference
Occurrence Weighted Weighted
Pascal C Pascal C Pascal C
ASSIGN 45 38 13 13 14 15
LOOP 5 3 42 32 33 26
CALL 15 12 31 33 44 45
IF 29 43 11 21 7 13
GOTO 3
Other 6 1 3 1 2 1

The procedure (function) call/return is the most time-consuming


operations in typical HLL programs

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RISC
CALL-RETURN BEHAVIOR

Call-return behavior as a function of nesting depth and time

Bharati Vidyapeeths Institute of Computer Applications and Management, New Delhi-63, by Dr. Deepali Kamthania U1.
137
RISC
REGISTER WINDOW APPROACH
Observations
Weighted Dynamic Frequency of HLL Operations
Procedure call/return is the most time consuming operations
Locality of Procedure Nesting
The depth of procedure activation fluctuates within a
relatively narrow range
A typical procedure employs only a few passed
parameters and local variables
Solution
Use multiple small sets of registers (windows), each assigned to
a different procedure
A procedure call automatically switches the CPU to use a
different window of registers, rather than saving registers in
memory
Windows for adjacent procedures are overlapped to allow
parameter passing
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RISC
OVERLAPPED REGISTER WINDOWS

R73 R25
Local to D
R64 R16
R63 R15 R31
Common to C and D
R58 R10 R26
R57 Proc D R25
Local to C
R48 R16
R47 R15 R31
Common to B and C
R42 R10 R26
R41 Proc C R25
Local to B
R32 R16
R31 R15 R31
Common to A and B
R26 R10 R26
R25 Proc B R25
Local to A
R16 R16
R15 R31 R15
Common Common to A and D
R10 R26 to D and A R10
R9 R9 Proc A
Common to all
procedures
R0 R0
Global
registers

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OVERLAPPED REGISTER WINDOWS
There are three classes of registers:
Global Registers
Available to all functions
Window local registers
Variables local to the function
Window shared registers
Permit data to be shared without actually needing to copy it
Only one register window is active at a time
The active register window is indicated by a pointer
When a function is called, a new register window is activated
This is done by incrementing the pointer
When a function calls a new function, the high numbered registers
of the calling function window are shared with the called function as
the low numbered registers in its register window
This way the callers high and the called functions low registers
overlap and can be used to pass parameters and results

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Cont
In addition to the overlapped register windows, the processor
has some number of registers, G, that are global registers
This is, all functions can access the global registers.
The advantage of overlapped register windows is that the
processor does not have to push registers on a stack to save
values and to pass parameters when there is a function call
Conversely, pop the stack on a function return
This saves
Accesses to memory to access the stack.
The cost of copying the register contents at all
And, since function calls and returns are so common, this
results in a significant savings relative to a stack-based
approach

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RISC
BERKELEY RISC I
- 32-bit integrated circuit CPU
- 32-bit address, 8-, 16-, 32-bit data
- 32-bit instruction format
- total 31 instructions
- three addressing modes:
register; immediate; PC relative addressing
- 138 registers
10 global registers
8 windows of 32 registers each
Berkeley RISC I Instruction Formats
Regsiter mode: (S2 specifies a register)
31 24 23 19 18 14 13 12 5 4 0
Opcode Rd Rs 0 Not used S2
8 5 5 1 8 5

Register-immediate mode (S2 specifies an operand)


31 24 23 19 18 14 13 12 0
Opcode Rd Rs 1 S2
8 5 5 1 13

PC relative mode
31 24 23 19 18 0
Opcode COND Y
8 5 19
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Cont
Register 0 was hard-wired to a value of 0.
There are eight memory access instructions
Five load-from-memory instructions
Three store-to-memory instructions.

The load instructions:


LDL load long
LDSU load short unsigned
LDSS load short signed
LDBU load byte unsigned
LDBS load byte signed
Where long is 32 bits, short is 16 bits and a byte is 8 bits
The store instructions:
STL store long
STS store short
STB store byte

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Cont
LDL Rd M[(Rs) + S2] load long

LDSU Rd M[(Rs) + S2] load short unsigned


LDSS Rd M[(Rs) + S2] load short signed

LDBU Rd M[(Rs) + S2] load byte unsigned


LDBS Rd M[(Rs) + S2] load byte signed

STL M[(Rs) + S2] Rd store long


STS M[(Rs) + S2] Rd store short
STB M[(Rs) + S2] Rd store byte
Here the difference between the lengths is
A long is simply loaded, since it is the same size as the register (32 bits).
A short or a byte can be loaded into a register
Unsigned - in which case the upper bits of the register are loaded with 0s.
Signed - in which case the upper bits of the register are loaded with the sign bit of
the short/byte loaded.

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INSTRUCTION SET OF BERKELEY RISC I
Opcode Operands Register Transfer Description
Data manipulation instructions
ADD Rs,S2,Rd Rd Rs + S2 Integer
add
ADDC Rs,S2,Rd Rd Rs + S2 + carry Add with carry
SUB Rs,S2,Rd Rd Rs - S2 Integer
subtract
SUBC Rs,S2,Rd Rd Rs - S2 - carry Subtract with carry
SUBR Rs,S2,Rd Rd S2 - Rs Subtract
reverse
SUBCR Rs,S2,Rd Rd S2 - Rs - carry Subtract with carry
AND Rs,S2,Rd Rd Rs S2 AND
OR Rs,S2,Rd Rd Rs S2 OR
XOR Rs,S2,Rd Rd Rs S2 Exclusive-OR
SLL Rs,S2,Rd Rd Rs shifted by S2 Shift-left
SRL Rs,S2,Rd Rd Rs shifted by S2 Shift-right logical
SRA Rs,S2,Rd Rd Rs shifted by S2 Shift-right arithmetic

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RISC
Cont
Opcode Operands Register Transfer Description
Data transfer instructions
LDL (Rs)S2,Rd Rd M[Rs + S2] Load long
LDSU (Rs)S2,Rd Rd M[Rs + S2] Load short unsigned
LDSS (Rs)S2,Rd Rd M[Rs + S2] Load short signed
LDBU (Rs)S2,Rd Rd M[Rs + S2] Load byte unsigned
LDBS (Rs)S2,Rd Rd M[Rs + S2] Load byte signed
LDHI Rd, Y Rd Y Load immediate high
STL Rd,(Rs)S2M[Rs + S2] Rd Store long
STS Rd,(Rs)S2M[Rs + S2] Rd Store short
STB Rd,(Rs)S2 M[Rs + S2] Rd Store byte
GETPSW Rd Rd PSW Load status word
PUTPSW Rd PSW Rd Set status word

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INSTRUCTION SET OF BERKELEY RISC I
Opcode Operands Register Transfer Description
Program control instructions
JMP COND,S2(Rs) PC Rs + S2 Conditional
jump
JMPR COND,Y PC PC + Y Jump
relative
CALL Rd,S2(Rs) Rd PC, PC Rs + S2 Call
subroutine& CWP CWP - 1
Change window
CALLR Rd,Y Rd PC, PC PC + Y Call
relative and
CWP CWP - 1 change
window
RET Rd,S2 PC Rd + S2 Return
and
CWP CWP + 1 change
window
CALLINT Rd Rd PC,CWP CWP - 1 Call an U1.
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RISC
CHARACTERISTICS OF RISC
RISC Characteristics
- Relatively few instructions
- Relatively few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction format
- Single-cycle instruction format
- Hardwired rather than microprogrammed control

Advantages of RISC

- VLSI Realization
- Computing Speed
- Design Costs and Reliability
- High Level Language Support

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RISC

ADVANTAGES OF RISC
VLSI Realization Example:
RISC I: 6%
Control area is considerably reduced RISC II: 10%
MC68020: 68%
general CISCs: ~50%

RISC chips allow a large number of registers on the chip


- Enhancement of performance and HLL support
- Higher regularization factor and lower VLSI design cost

The GaAs VLSI chip realization is possible

Computing Speed
- Simpler, smaller control unit faster
- Simpler instruction set; addressing modes; instruction format
faster decoding
- Register operation faster than memory operation
- Register window enhances the overall speed of execution
- Identical instruction length, One cycle instruction execution
suitable for pipelining faster

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RISC
ADVANTAGES OF RISC
Design Costs and Reliability
- Shorter time to design
reduction in the overall design cost and
reduces the problem that the end product will
be obsolete by the time the design is completed
- Simpler, smaller control unit
higher reliability
- Simple instruction format (of fixed length)
ease of virtual memory management

High Level Language Support


- A single choice of instruction
shorter, simpler compiler
- A large number of CPU registers
more efficient code
- Register window
Direct support of HLL
- Reduced burden on compiler writer

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CONCLUSIONS

CPU Organizations
Addressing Modes
Address Instructions
Classification of computer instructions
RISC/CISC

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OBJECTIVE QUESTIONS
1. A CPUs microinstruction format has five separate control fields. The number of
micro operations in each fields are as follows F1=4, F2 = 4, F3 = 3, F4 = 12, F5
= 21
i. What is the total length of microinstrcution needed to accommodate the
five control fields
ii. If pure horizontal microprogramming is followed without encoding, what will
be the length of microinstruction?
2. Pick out the incorrect RTL statement and indicate the problems
1. PC:= MAR, PC:= PC+1 2. MR:=1, Pc:=PC+1
3. NOOP instruction requires nothing (no action) to be performed for the
instruction. This is true for macro operation level but false for the
microoperation level. The control unit must perform one microoperation which
is necessary for any instruction. Identify the essential micro operation which is
performed for NOOP instruction.
4. Is nano and micro programming same?
5. The address of stack is stored in _____________
6. In ___________________addressing mode the content of PC is added to
address part of the instruction in order to obtain the effective address
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Cont
7. Control word specifies ________________
8. Memory unit that stores the control word is ___________
9. ________ is program which convert symbolic language into machine code.
10. ________ is also called nexr address generator.
11. The instructions which copy information from one location to another either in
the processors internal register set or in the external main memory are called
a. Data transfer instructions. b. Program control instructions.
c. Input-output instructions. d. Logical instructions.
12. If the value V(x) of the target operand is contained in the address field itself,
the addressing mode is
a. immediate. b. direct. c. indirect. d. implied.
13. A microprogram sequencer
a. generates the address of next micro instruction to be executed.
b. generates the control signals to execute a microinstruction.
c sequentially averages all microinstructions in the control memory.
d. enables the efficient handling of a micro program subroutine.

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Cont
14. During what CPU cycle is an instruction moved from primary
storage to the control unit?
a. fetch
b. execution
c. access
d. refresh

15. What type of processor does not directly implement instructions that combine data
movement and manipulation?
a. CISC
b. RISC
c. microprocessor
d. PSW

16. When the control unit fetches an instruction from memory, it stores
it in the ____.
a. instruction pointer
b. program status word
c. op code
d. instruction register

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Cont
17. Which of the following is a storage location that holds inputs and
outputs for the ALU?
a. Control unit
b. ALU
c. I/O device
d. Register

18. The ____ tests the bit values in the source location and places copies
of those values in the destination location.
a. LOAD
b. MOVE
c. STORE
d. ADD

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SHORT QUESTIONS
1. The instruction length and operand address field is 36 bits and 14 bits
respectively. If two operand instructions of 240 numbers are used, then
how many one operand instructions are possible?
2. The stack based CPU dont have registers for storing the operands. Can we
conclude that the stack based CPU has less hardware circuit and cheaper
than register based CPU?
3. The instruction format of a CPU is designed for the two types (a) op-code
and three fields for register address; (b) op-code and one field for memory
address. Identify different formats for instructions.
4. Difference between horizontal and vertical instruction format.
5. What is firmware? How it is different from software and hardware?
6. A register based CPU can be viewed as multiple accumulators based CPU.
Justify this statement
7. A micro programmed CPU has 1K words in the control memory. Each
instruction needs 8 microinstructions. Assuming that the op-code in the
macro instruction is of 5 bits length, propose a mapping scheme to
generate control memory address for the op-code.

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Cont

8. Name some functions of control unit.


9. What is the difference between internal and software interrupts?
10. A computer has 32 bit instructions and 12 bit addresses. If there are 250
two address instruction, how many one address instruction can be
formulated?
11. What is the Fetch routine in Micro programmed control unit
12. The instructions are classified on the basis of following factors
1. Op-code: ______________
2. Data:_________________,__________________, etc
3. Operand location: __________,______________
4. Operand addressing: ______________________
5. Instruction length:_______,_________,_____
6. No. of address field____________,________,_______

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LONG QUESTIONS

1. Write an assembly language program to derive the expression X=(A+B)-


(C+D) for an accumulator, register and stack based CPU
2. What is addressing mode? Discuss different types of addressing modes with
its advantages and disadvantages.
3. A program has three jump instructions in three consecutive words (locations)
in memory: 0111, 1000and 1001.The corresponding jump addresses are
1001, 0111, 0111 respectively. Suppose we load 0111.Initially in PC and start
the CPU, how many times will the instruction in location be fetched and
executed?
4. A 32-bit CPU has 16-bit instruction and 12-bit memory address. Its memory is
organized as 4K of 32-bits each. Each memory word stores two instructions.
The instruction format has 4-bits for op-code. The CPUs instruction register
can accommodate two instructions. Suggest a design strategy for the
instruction cycle sequence.
5. What is the basic difference between a branch instruction, a call subroutine
instruction, and a program interrupt? Explain various types of interrupts and
give examples of each.

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Cont..
6. A processor has following hardware configuration
a. No. of registers=8
b. ALU operations: arithmetic 8,logic 8
c. Shifter : 4 operations
d. Bus: single bus
Design the microinstruction format for this CPU
7. A digital computer has a common bus system for 12 registers of 9 bits each. The bus
is constructed with multiplexers.
a. How many selection inputs are there in each multiplexer?
b. What size of multiplexers are needed?
c. How many multiplexers are there in the bus?
d. Draw a diagram of the bus system using three-state buffers and a
decoder instead of multiplexers?
8.The system uses a control memory of 1024 words of 32 bits each. The
microinstruction has three fields for micro-operations. select a status bit and Brach
address field. The micro-operation field has 16 bits.
a. How many bits are there in the branch address field and select field?
b. If there are 16 status bits in the system, how many bits of the branch logic
are used to select a status bit?
c. How many bits are left to select the input to the multiplexers?

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Cont..
9. Write micro operation for BSA and ISZ
10. A computer has following registers PC(12 bits), MAR(16), MBR(12),
I(1),OPR(3), E(1), AC(16) and six timing signal t0 to t5 and one flip-flop F for
cycle control. Fetch cycle is performed when F=0 and execute cycle when
F=1. List the micro-operations and control functions for the computer
(i) When F=0
(ii) For Executing XOR, SWAP (AC and memory Word) ADD (M M+AC)
11. A digital system has 16 registers, each with 32-bits.It is necessary to provide
parallel data transfer from each register to every other register
a. How many lines are needed for direct parallel transfer?
b. If we need to link these register to a common bus
c. How many Multiplexer will be required?
d. How many input lines are required for each multiplexer
12. In a seven register bus organization of CPU the propagation delays are given,
30s for multiplexer, 60 ns to perform the add operation in the ALU and 20 ns
in the destination decoder, and 10 ns to clock the data into destination
register. What is the minimum cycle time that can be used for the clock

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RESEARCH PROBLEM
1. What are the differences between CISC and RISC architectures?
Which types of applications are properly suited for each of these
categories of architecture?
Compare and contrast CISC architecture and RISC architecture. Make
sure to include the strengths and weaknesses of each as well as
applications to which they would be most suited. You may also
compare/contrast them with any architecture that may be considered as
future replacements for either or both of these two.

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REFERENCES

1. Hayes P. John, Computer Architecture and Organisation, McGraw


Hill Comp., 1988.
2. Mano M., Computer System Architecture, Prentice-Hall Inc. 1993.
3. Patterson, D., Hennessy, J., Computer Architecture - A
Quantitative Approach, second edition, Morgan Kaufmann
Publishers, Inc. 1996;
4. Stallings, William, Computer Organization and Architecture, 5 th
edition, Prentice Hall International, Inc., 2000.
5. Tanenbaum, A., Structured Computer Organization, 4th ed.,
Prentice- Hall Inc. 1999.
6. Hamacher, Vranesic, Zaky, Computer Organization, 4th ed.,
McGraw Hill Comp., 1996.

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