EEE3410 Microcontroller Applications Department of Electrical Engineering

EEE3410 Microcontroller Applications
Department of Electrical Engineering
│ Lecture 4 │
The 8051 Architecture
© Vocational Training Council, Hong Kong. Week 4 1

In this Lecture ……
Overview
General physical & operational features
Block diagram
Pin assignments
Logic symbol
Hardware description
Pin description
Read-modify-write port instructions

Overview of the 8051
Made by Intel in 1981

An 8-bit, single-chip microcontroller optimized
for control applications
128 bytes RAM, 4096 bytes (4KB) ROM, 2
timers, 1 serial port, 4 I/O ports
40 pins in a dual in-line package (DIP) layout

General Physical Features

4KB ROM
128 bytes internal RAM
4 register banks of 8 bytes each (R0-R7)
16 bytes of bit-addressable area
80 bytes of general purpose memory
Four 8-bit I/O ports (P0-P3)
Two 16-bit timers (Timer0 & Timer1)
One serial receiver-transmitter interface
Five interrupt sources (2 external & 3 internal)
One oscillator (generates clock signal)
General Operational Features
Memory of 8051 can be increased externally:

Increase memory space for codes (programs)
by 64K
Increase memory space for data by 64K
Boolean instructions work with 1 bit at a time
Assume clock frequency = 12MHz, it takes
about 4 s (i.e. 4 x 10-6s) to carry out a 8-bit
multiplication instruction

The 8051 Block Diagram

External Interrupts
4K byte Timer 1
128 byte Counter
Interrupt Control ROM RAM Timer 0 Inputs
CPU
Bus Serial
OSC I/O Ports
Control Port
TXD RXD
P0 P2 P1 P3
(Address/Data)

The 8051 Pin Assignments

P1.0 1 40 VCC
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 8051 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
RST 9 32 P0.7 (AD7)
(RXD) P3.0 10 31 EA/VPP
(TXD) P3.1 11 30 ALE/PROG
(INT0) P3.2 12 29 PSEN
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)

The 8051 Logic Symbol
VSS VCC RST
P0.7
XTAL1 P0.6 P
P0.5 O ADDRESS
P0.4 R AND
XTAL2 P0.3 DATA BUS
P0.2 T
P0.1 0
P0.0
EA
PSEN P1.7
P1.6 P
ALE P1.5 O
P1.4 R
P1.3 T
P1.2 1
P1.1
P1.0
RxD P3.7 P2.7

TxD P P3.6 P2.6 P ADDRESS
SECONDARY INT0 O P3.5 P2.5 O BUS
INT1 R P3.4 P2.4 R
FUNCTIONS T0 P3.3 P2.3
T P3.2 P2.2 T
T1 2
WR 3 P3.1 P2.1
RD P3.0 P2.0

Hardware Description
1. Oscillator circuit
2. Program counter (PC)
3. Data pointer (DPTR)
4. Accumulator (“A”) register
5. B register
6. Flags
7. Program status word (PSW)
8. Internal memory (ROM, RAM, additional
memory)
9. Stack & stack pointer (SP)
10. Special function register (SFR)
Oscillator Circuit
A single machine cycle
The heart of the 8051 consists of 12 crystal pulses !
Produces clock pulses
Synchronize all 8051’s internal operations

Machine Cycle
 Machine cycle is the basic repetitive process that the CPU
performs once it is powered on. A machine cycle consists of
a fixed number of clock cycles (pulses). It is different for
different kinds of CPU.
 The 8051 family needs 12 clock cycles for a machine cycle.
 The CPU takes one or more machine cycles to complete an
instruction. More complex instructions require more number
of machine cycles to complete the instruction. The number of
machine cycles of the 8051 instructions are ranging from 1 to
4.

Example 4-1
Find the elapse time of the machine cycle for:
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz
(c) XTAL = 20 MHz
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz
Machine cycle = 1 / 921.6 kHz = 1.085 s
(b) 16 MHz / 12 = 1.333 MHz
Machine cycle = 1 / 1.333 MHz = 0.75 s
(c) 20 MHz / 12 = 1.667 MHz
Machine cycle = 1 / 1.667 MHz = 0.60 s

Program Counter (PC)

PC is a 16-bit register
PC is the only register that does not have an
internal address
Holds the address of the memory location to fetch
the program instruction
Program ROM may be on the chip at addresses
0000H to 0FFFH (4Kbytes), external to the chip for
addresses that exceed 0FFFH
Program ROM may be totally external for all
addresses from 0000H to FFFFH
PC is automatically incremented (+1) after every
instruction byte is fetched

Data Pointer (DPTR)

DPTR is a 16-bit register
DPTR is made up of two 8-bit registers: DPH and DP
L
DPTR holds the memory addresses for internal and
external code access and external data access
(eg. MOVC A,@A+DPTR MOVX A,@DPTR MOVX @DPTR,A )
DPTR is under the control of program instructions a
nd can be specified by its 16-bit name, or by each i
ndividual byte name, DPH and DPL
DPTR does not have a single internal address; DPH
and DPL are each assigned an address (83H and 82
H)
Accumulator (A Register)
Most versatile CPU register and is used for many

operations, including addition, integer
multiplication and division, and Boolean bit
manipulations
A register is also used for all data transfer
between the 8051 and any external memory

B Register
B register is used with the A register for multi

plication and division operations
(eg. MUL AB DIV AB)
No other special function other than as a loca
tion where data may be stored

Flags
Flags are 1-bit registers provided to store the results
of certain program instructions
Other instructions can test the condition of the flags
and make decisions based on the flag states
Flags are grouped inside the program status word
(PSW) and the power control (PCON) registers for
convenient addressing
Math flags: respond automatically to the outcomes of
math operations (CY, AC, OV, P)
User flags: general-purpose flags that may be used by
the programmer to record some event in the program
(F0, GF0, GF1)
Program Status Word (PSW)
PSW contains the math flags, user program flag

F0, and the register select bits (RS1, RS0) that
identify which of the four general-purpose
register banks is currently in use by the program
7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV -- P


Bit Symbol Function
7 CY Carry Flag; used in arithmetic, JUMP,
ROTATE, and BOOLEAN instruction
6 AC Auxiliary carry flag; used for BCD arithmetic
5 F0 User flag 0
4 RS1 Register bank select bit 1
3 RS0 Register bank select bit 0
2 OV Overflow flag; used in arithmetic instructions
1 -- Reserved for future use
0 P Parity flag; shows parity of register A: 1 =
Odd Parity
Instruction that Affect Flag Bits

Instruction CY OV AC Instruction CY OV AC
ADD X X X SETB C 1
ADDC X X X CLR C 0
SUBB X X X CPL C X
MUL 0 X ANL C, bit X
DIV 0 X ANL C, /bit X
DA X ORL C, bit X
RRC X ORL C, /bit X
RLC X CJNE X
MOV C, bit X Note: X can be 0 or 1
Internal Memory
A functioning computer must have memory for
program code bytes, commonly in ROM, and RAM
memory for variable data that can be altered as the
program runs
8051 has internal RAM (128 bytes) and ROM
(4Kbytes)
8051 uses the same address but in different
memories for code and data
Internal circuitry access the correct memory based
on the nature of the operation in progress
Can add memory externally if needed
8051 Internal RAM Organisation

1F R7
1E R6 7F
1D R5
Bank 3
1C R4
1B R3
1A R2
19 R1
18 R0
17 R7
16 R6
15 R5
Bank 2
14 R4
13 R3
12 R2
11 R1
10 R0
0F R7 2F 7F 78
0E R6 2E 77 70
Bank 1
0D R5 2D 6F 68
0C R4 2C 67 60
0B R3 2B 5F 58
0A R2 2A 57 50
09 R1 29 4F 48
08 R0 28 47 40
07 R7 27 3F 38
06 R6 26 37 30
05 R5 25 2F 28
Bank 0
04 R4 24 27 20
03 R3 23 1F 18
02 R2 22 17 10
01 R1 21 0F 08
00 R0 20 07 00 30
Working Registers Bit Addressable General Purpose

Example 2-5
State the contents of RAM locations after the following program:
MOV R0, #99H
MOV R1, #85H
MOV R2, #3FH
MOV R7, #63H
MOV R5, #12H
After the execution of the above program we have the following:

RAM location 0 has value 99H RAM location 1 has value 85H
RAM location 2 has value 3FH RAM location 7 has value 63H
RAM location 5 has value 12H


Bank Select Bits, RS1, & RS0 to select 1 of 4 register bank

Example 2-6
Repeat Example 2-5 using RAM addresses instead of register
names.
This is called direct addressing mode and uses the RAM

address location for the destination address.
MOV 00, #99H
MOV 01, #85H
MOV 02, #3FH
MOV 07, #63H
MOV 05, #12H

Example 2-7
State the contents of RAM locations after the following program:
SETB PSW.4
MOV R0, #99H
MOV R1, #85H
MOV R2, #3FH
MOV R7, #63H
7 6 5 4 3 2 1 0
MOV R5, #12H
PSW CY AC F0 RS1 RS0 OV -- P
By default, PSW.3=0 and PSW.4=0; therefore, the instruction “SETB

PSW.4” sets RS1=1 and RS0=0, thereby selecting register bank 2.
Register bank 2 uses RAM locations 10H – 17H. After the execution of
the above program we have the following
RAM location 10 has value 99H RAM location 11 has value 85H
RAM location 12 has value 3FH RAM location 17 has value 63H
RAM location 15 has value 12H
Stack and Stack Pointer (SP)

SP is a 8-bit register used to hold an internal RAM addr
ess that is called the “top of the stack”
Stack refers to an area of internal RAM that is used in c
onjunction with certain opcodes to store and retrieve d
ata quickly
SP holds the internal RAM address where the last byte o
f data was stored by a stack operation
When data is to be placed on the stack, the SP increme
nts before storing data on the stack so that the stack g
rows up as data is stored
As data is retrieved from the stack, the byte is read fro
m the stack, and then the SP decrements to point to th
e next available byte of stored data
SP = 07H after reset
Stack Operation
Store Data Get Data
SP = 0A Address 0A SP = 0A
Store Data Get Data

SP = 09 Address 09 SP = 09
Store Data Get Data

Storing Data on the Stack Internal RAM Getting Data From the Stack
(Increment then store) (Get then decrement)

Example 2-8
Show the stack and stack pointer for the following. Assume the
default stack area.
MOV R6, #25H
MOV R1, #12H
MOV R4, #0F3H
PUSH 6
PUSH 1
PUSH 4
After PUSH 6 After PUSH 1 After PUSH 4

0B 0B 0B 0B
0A 0A 0A 0A F3
09 09 09 12 09 12
08 08 25 08 25 08 25
SP = 07 SP = 08 SP = 09 SP = 0A

Example 2-9
Examine the stack, show the contents of the registers and SP after
execution of the following instruction. All values are in hex.
POP 3 ;POP stack into R3
After POP 3 After POP 5 After POP 2

0B 54 0B 54 0B 54 0B 54
0A F9 0A F9 0A F9 0A F9
09 76 09 76 09 76 09 76
08 6C 08 6C 08 6C 08 6C
Start SP = 0B SP = 0A SP = 09 SP = 08
05 ?? 05 ?? 05 F9 05 F9
04 ?? 04 ?? 04 ?? 04 ??
03 ?? 03 54 03 54 03 54
02 ?? 02 ?? 02 ?? 02 76

Example 2-10
Show the stack and stack pointer for the following.
MOV SP, #5FH
MOV R2, #25H
MOV R1, #12H
MOV R4, #0F3H
PUSH 2
PUSH 1
PUSH 4
After PUSH 2 After PUSH 1 After PUSH 4

63 63 63 63
62 62 62 62 F3
61 61 61 12 61 12
60 60 25 60 25 60 25
Start SP = 5F SP = 60 SP = 61 SP = 62

Special Function Registers (SFR)
8051 has 21 SFRs which occupy the addresses

from 80H to FFH (128bytes)
Not all of the addresses from 80H to FFH are
used for SFRs
Attempt to use the “empty” addresses may g
et unpredictable result

Special Function Register Map

Bit addressable

Value of SFR at Reset

Internal ROM
Internal ROM occupies the code address space
from 0000H to 0FFFH (Size = 4K byte)
Program addresses higher than 0FFFH will
automatically fetch code bytes from external
program memory
Code bytes can also be fetched exclusively from
an external memory by connecting the external
access pin (EA) to ground

Some Important Pins
VCC (pin 40 - provides supply voltage of +5V)

GND (pin 20)
XTAL1 & XTAL2 (pins 19 & 18 - to crystal and
then caps)
RST (pin 9- reset)
EA (pin 31 - external access)
PSEN (pin 29 - program store enable)
ALE (pin 30 - address latch enable)
Ports 0-3

I/O Ports (P0 - P3)

One of the most useful features of the 8051 is that
it consists of 4 I/O ports (P0 - P3)
All ports are bidirectional (they can take input and t
o provide output)
All ports have multiple functions (except P1)
All ports are bit addressable
On RESET all the ports are configured as output
When a bit latch is to be used as an input, a “1” m
ust be written to the corresponding latch by the pr
ogram to configure it as input (eg. MOV P1, #0FFH)

Port 0
Occupies a total of 8 pins (Pins 32-39)
Can be used for :
Input only
Output only
Input and output at the same time (i.e. some
pins for input and the others for output)
Can be used to handle both address and data
Need pull-up resistors

Port 0 as an Output Port

The following code will continuously send out to port
0 the alternating values 55H and AAH
MOV A, #55H
BACK: MOV P0, A
ACALL DELAY
CPL A
SJMP BACK

Port 0 as an Input Port

In the following code, port 0 is configured first
as an input port by writing 1s to it, and then
data is received from that port and sent to P1
MOV A, #0FFH
MOV P0, A
BACK: MOV A, P0
MOV P1, A
SJMP BACK

Dual Role of Port 0

When connecting an 8051 to an external mem
ory, port 0 provides both address and data (A
D0 – AD7)
When ALE = 0, it provides data D0 – D7
When ALE = 1, it provides data A0 – A7
ALE is used for demultiplexing address and da
ta with the help of
a 74LS373 latch

Port 1
Can be used as input or output
Does not need any pull-up resistors
Upon reset, port 1 is configured as an
output port
No alternative functions


MOV A, #55H
BACK: MOV P1, A
ACALL DELAY
CPL A
SJMP BACK


In the following code, port 1 is configured first as an
input port by writing 1s to it, and then data is received
from that port and saved in R7, R6, and R5
MOV A, #0FFH
MOV P1, A
MOV A, P1
MOV R7, A
ACALL DELAY
MOV A, P1
MOV R6, A
ACALL DELAY
MOV A, P1
MOV R5, A

Port 2

Similar function as Port 1
Upon reset, port 2 is configured as an output
port


MOV A, #55H
BACK: MOV P2, A
ACALL DELAY
CPL A
SJMP BACK


In the following code, port 2 is configured first as an
input port by writing 1s to it, and then data is received
from that port and sent to P1
MOV A, #0FFH
MOV P2, A
BACK: MOV A, P2
MOV P1, A
SJMP BACK

Dual Role of Port 2

When connecting an 8051 to an external
memory, port 2 provides both address (A8 –
A15)
It is used along with P0 to provide the 16-bit
address
When P2 is used for the upper 8 bits of the 16-
bit address, it cannot be used for I/O

Port 3
Similar function as Port 1 and Port 2
Upon reset, port 3 is configured as an output port
Pins can be individually programmable for other uses
Most commonly be used to provide some important signals
(e.g. interrupts)

Port 3 Alternate Functions

P3 Bit Function Pin
P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17

Read-Modify-Write Feature
A method used to access the 8051 ports
Combining all 3 actions in a single instructions :
Read the data at the port
Modify (do operation on) the data at the port
Write the results to the port Example:
ANL P1, A
ORL P2, A
MOV P1, #55H XRL P3, A
AGAIN: XRL P1, #0FFH JBC P1.1, LABEL
CPL P3.0
ACALL DELAY INC P2
SJMP AGAIN DEC P2
DJNZ P3, LABEL

Single-bit Addressability of Ports

One of the most powerful features of the
8051
Access only one or several bits of the port
instead of the entire 8 bits
BACK: CPL P1.2

ACALL DELAY
SJMP BACK

Example 4-2
Write a program to perform the following:
(a) Keep monitoring the P1.2 bit until it becomes high;
(b) When P1.2 becomes high, write value 45H to port 0; and
(c) Send a high-to-low (H-to-L) pulse to P2.3
SETB P1.2 ; config pin P1.2 as input
MOV A, #45H
AGAIN:
JNB P1.2, AGAIN ; wait until P1.2=1
; now P1.2 = 1
MOV P0, A
SETB P2.3
CLR P2.3
Summary
General physical & operational features

8051 hardware description
8051 pin description
Read-modify-write port instructions

Review Questions
1. In the 8051, the program counter is _________ bits wide.
2. True or false. Every member of the 8051 family, regardless
of the maker, wakes up at memory 0000H when it is powere
d up.
3. At what ROM location do we store the first opcode of an 805
1 program?
4. The instruction “MOV A, #44H” is a ______-byte instruction.
5. What is the ROM address space for the 8052 chip?
6. The flag register in the 8051 is called __________.
7. What is the size of the flag register in the 8051?
8. Which bits of the PSW register are user-definable?

Review Questions
9. Find the CY and AC flag bits for the following code.
MOV A, #0FFH
ADD A, #01
10. Find the CY and AC flag bits for the following code.
MOV A, #0C2H
ADD A, #3DH
11. What is the size of the SP register?
12. With each PUSH instruction, the stack pointer register (SP) is
_______ (incremented/decremented) by 1.
13. With each POP instruction, the SP _____
(incremented/decremented) by 1.
14. ON power up, the 8051 uses RAM location _____ as the first
location of the stack.

 Review Questions
15. On power up, the 8051 uses bank ____ for registers R0 – R7.
16. On power up, the 8051 uses RAM locations _____ to _____
for register R0 – R7 (register bank 0).
17. Which register bank is used if we alter RS0 and RS1 of the
PSW by the following two instruction?
SETB PSW.3
SETB PSW.4
18. In Question 17, what RAM locations are used for register R0
– R7?

 Read reference
The 8051 Microcontroller and Embedded Systems -
Using Assembly and C, Mazidi
 Chapter 8 P.217 – P.227
 The 8051 Microcontroller – Hardware, Software and
Interfacing, James W. Stewart
 Chapter 1 P.1 – P.16
 Chapter 2 P.19 – P.35

EEE3410 Microcontroller Applications Department of Electrical Engineering

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EEE3410 Microcontroller Applications

Department of Electrical Engineering

The 8051 Architecture

© Vocational Training Council, Hong Kong. Week 4 1

© Vocational Training Council, Hong Kong. Week 4 2

Overview of the 8051

Made by Intel in 1981

© Vocational Training Council, Hong Kong. Week 4 3

General Physical Features

General Operational Features

Memory of 8051 can be increased externally:

© Vocational Training Council, Hong Kong. Week 4 5

The 8051 Block Diagram

© Vocational Training Council, Hong Kong. Week 4 6

The 8051 Pin Assignments

© Vocational Training Council, Hong Kong. Week 4 7

The 8051 Logic Symbol

VSS VCC RST

RxD P3.7 P2.7

© Vocational Training Council, Hong Kong. Week 4 8

© Vocational Training Council, Hong Kong. Week 4 10

© Vocational Training Council, Hong Kong. Week 4 11

© Vocational Training Council, Hong Kong. Week 4 12

Program Counter (PC)

© Vocational Training Council, Hong Kong. Week 4 13

Data Pointer (DPTR)

Most versatile CPU register and is used for many

© Vocational Training Council, Hong Kong. Week 4 15

B register is used with the A register for multi

© Vocational Training Council, Hong Kong. Week 4 16

Program Status Word (PSW)

PSW contains the math flags, user program flag

© Vocational Training Council, Hong Kong. Week 4 18

Program Status Word (PSW)

Instruction that Affect Flag Bits

8051 Internal RAM Organisation

Working Registers Bit Addressable General Purpose

© Vocational Training Council, Hong Kong. Week 4 22

After the execution of the above program we have the following:

© Vocational Training Council, Hong Kong. Week 4 23

Program Status Word (PSW)

© Vocational Training Council, Hong Kong. Week 4 24

This is called direct addressing mode and uses the RAM

© Vocational Training Council, Hong Kong. Week 4 25

By default, PSW.3=0 and PSW.4=0; therefore, the instruction “SETB

Stack and Stack Pointer (SP)

Store Data Get Data

Store Data Get Data

© Vocational Training Council, Hong Kong. Week 4 28

After PUSH 6 After PUSH 1 After PUSH 4

© Vocational Training Council, Hong Kong. Week 4 29

After POP 3 After POP 5 After POP 2

© Vocational Training Council, Hong Kong. Week 4 30

After PUSH 2 After PUSH 1 After PUSH 4

© Vocational Training Council, Hong Kong. Week 4 31

Special Function Registers (SFR)

8051 has 21 SFRs which occupy the addresses

© Vocational Training Council, Hong Kong. Week 4 32

Special Function Register Map

© Vocational Training Council, Hong Kong. Week 4 33

Value of SFR at Reset

© Vocational Training Council, Hong Kong. Week 4 34