ASIC Design Flow

1. Design entry - Using a hardware description

language ( HDL ) or schematic entry
 1. Design entry - Using a hardware description
language ( HDL ) or schematic entry
2. Logic synthesis - Produces a netlist - logic
cells and their connections
 1. Design entry - Using a hardware description
language ( HDL ) or schematic entry
2. Logic synthesis - Produces a netlist - logic cells and
their connections
3. System partitioning - Divide a large system into
ASIC-sized pieces
 1. Design entry - Using a
hardware description language
( HDL ) or schematic entry
2. Logic synthesis - Produces a
netlist - logic cells and their
connections
3. System partitioning - Divide
a large system into ASIC-sized
pieces
4. Prelayout simulation - Check
to see if the design functions
correctly
 1. Design entry - Using a
hardware description language
( HDL ) or schematic entry
2. Logic synthesis - Produces a
netlist - logic cells and their
connections
3. System partitioning - Divide
a large system into ASIC-sized
pieces
4. Prelayout simulation - Check
to see if the design functions
correctly
5. Floorplanning - Arrange the
blocks of the netlist on the chip
 1. Design entry - Using a
hardware description language
( HDL ) or schematic entry
2. Logic synthesis - Produces a
netlist - logic cells and their
connections
3. System partitioning - Divide
a large system into ASIC-sized
pieces
4. Prelayout simulation - Check
to see if the design functions
correctly
5. Floorplanning - Arrange the
blocks of the netlist on the chip
6. Placement - Decide the
locations of cells in a block
 1. Design entry - Using a
hardware description language
( HDL ) or schematic entry
2. Logic synthesis - Produces a
netlist - logic cells and their
connections
3. System partitioning - Divide
a large system into ASIC-sized
pieces
4. Prelayout simulation - Check
to see if the design functions
correctly
5. Floorplanning - Arrange the
blocks of the netlist on the chip
6. Placement - Decide the
locations of cells in a block
7. Routing - Make the
connections between cells and
blocks
 1. Design entry - Using a
hardware description language
( HDL ) or schematic entry
2. Logic synthesis - Produces a
netlist - logic cells and their
connections
3. System partitioning - Divide
a large system into ASIC-sized
pieces
4. Prelayout simulation - Check
to see if the design functions
correctly
5. Floorplanning - Arrange the
blocks of the netlist on the chip
6. Placement - Decide the
locations of cells in a block
7. Routing - Make the
connections between cells and
blocks
8. Extraction - Determine the
resistance and capacitance of
the interconnect
 1. Design entry - Using a
hardware description language
( HDL ) or schematic entry
2. Logic synthesis - Produces a
netlist - logic cells and their
connections
3. System partitioning - Divide
a large system into ASIC-sized
pieces
4. Prelayout simulation - Check
to see if the design functions
correctly
5. Floorplanning - Arrange the
blocks of the netlist on the chip
6. Placement - Decide the
locations of cells in a block
7. Routing - Make the
connections between cells and
blocks
8. Extraction - Determine the
resistance and capacitance of
the interconnect
9. Postlayout simulation -
Check to see the design still
works with the added loads of
the interconnect
 Economics of ASICs

On a parts only basis, an FPGA is more expensive per-gate than an MGA,

which is in turn more expensive than a CBIC
The key is that the fixed cost of the CBIC is higher than the MGA which
is higher than the FPGA
Design cost
Fabrication cost
Total product (or part) cost is a function of fixed cost, variable cost, and
the number of products (parts) sold:
total part cost = fixed part cost + variable cost per part X volume of parts

Example, assume:
FPGA fixed cost is $21,800, part cost is $39
MGA fixed cost is $86,000, part cost is $10
CIBC fixed cost is $146,000, part cost is $18