VHDL- Control

Statements

By:
Dr. Gaganpreet Kaur
Behavioral Modeling
primary construct used for behavioral
modeling- Process.
statements written inside a process are
sequential though process statement in itself
is concurrent statement.

[ Processlabel]: PROCESS(Sensitivity List)

Variable , signal declarations;(local to the process) --- declarative region of process

BEGIN
Sequential statements1;
Sequential statement 2;

Sequential statement n;

END PROCESS [Process label];

Process
Sensitivity list contains the list of signals to
which the process is sensitive.
The process suspends after executing the last
sequential statement inside the process and
waits for another event to occur on a signal in
the sensitivity list.
declared inside the architecture body
identified with an optional process label
followed by colon and then keyword PROCESS
Process
declarative section -all the declarations of
signals, variables, constants with scope local
to the process are declared
other is executable part marked with
keyword BEGIN inside the process where all
the executable statements are written in
sequence in which they are expected to be
executed.
Finally every process ends with keyword END
PROCESS followed by optional process label,
if any.
Variables
Used for local storage in a process and
subprograms
declared and used inside a process
/subprograms
Variable assignment uses :=

[ Process label]: PROCESS(Sensitivity List)

VARIABLE var1[,var2]:TYPE:=intial_value --- declarative region of process
BEGIN
Statements;
END PROCESS [ Process label];
Wait Statement
gives the designer ability to suspend the
sequential execution of a process
enables designer to delay any process by a
specific amount
Three types of Wait Statements:
WAIT ON signal change
WAIT UNTIL an expression is true
WAIT FOR a specific amount of time
WAIT statement and SENSITIVITY LIST
cannot be present simultaneously in any
process.
Wait Statement
1. WAIT ON signal1[,signal2];

2WAIT UNTIL Boolean Expression;

3WAIT FOR time expression;

or combined form

4WAIT ON signal UNTIL Boolean Expression FOR time expression;

Examples:
WAIT ON A,B;

WAIT UNTIL enable=1;

WAIT FOR 10ns;

WAIT ON A UNTIL enable=1 FOR 10ns;

Sequential Statements
If Statement
1 IF condition THEN ---SIMPLE IF
Statements;.
END IF;
2. IF condition THEN --- IF ELSE
Statements;.
ELSE
Statements;.
END IF;
3. IF condition THEN ---- IF-ELSIF LADDER
Statements;.
ELSIF condition THEN
Statements;
ELSE
Statements;
END IF;
Continued.Case Statement

CASE expression IS
WHEN choice1 => Statements;.
WHEN choice2 => Statements;

WHEN OTHERS => Statements; -- default

value
END CASE;
Continued.
Loop statements
used when an operation needs to be
repeated

1. FOR identifier IN RANGE LOOP ---FOR LOOP

Statements;
END LOOP;
2. WHILE condition LOOP --- WHILE LOOP
Statements;
END LOOP;
3. LOOP --- SIMPLE LOOP
Statements;
END LOOP;
Continued.
Exit Statement
used to terminate the loop during the
execution of the LOOP statement
The control transfer to the statement
outside the LOOP statement

LOOP
EXIT or EXIT [LOOP LABEL] or EXIT WHEN condition;
END LOOP;
Continued.
NEXT statement
Skip a set of sequential statements or a loop
iteration.
all the statements after NEXT inside the
loop are skipped and processing jumps to
next iteration ,if any .
LOOP
Statement1;
NEXT or NEXT WHEN condition;
Statement2;
.
END LOOP;
Continued.
NULL
no action statement used when after certain
condition is met no action is required to be
performed
in CASE statement when for a particular
choice no action is to be taken NULL
statement is used.
Sequential VHDL code
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY my_ff IS
PORT (D,clk,reset:in std_logic; Q:out std_logic);
END my_ff;
ARCHITECTURE synch OF my_ff IS
begin
process (clk,reset)
begin
if reset='1' then
Q <='0';
elsif clk='1' and clk'EVENT then
Q<=D;
end if;
end process;
end synch;
Explanation
The source code shown implements a D flip flop
that is rising edge triggered and uses
asynchronous reset

The rising edge is detected by the following

statement:
elsif clk='1' and clk'EVENT then Q<=D;

This statement says that if clk has a current value

of 1 and if there has been an event on the clk line,
assign Q the value of D

Asynchronous reset is achieved by first checking if

reset has a value 1
Conditional assignment
statements
Two types of conditional assignment control
statements in concurrent style ;
are used to check conditions in dataflow
style:
WHEN-ELSE conditional statement
WITH-WHEN-ELSE conditional assignment
When-Else
conditional selection statement

checks the condition and assigns value to

output if condition is true

else next condition is checked and so on.

Output <= Val1 WHEN [ after time expression] condition1 ELSE

Val2 WHEN[ after time expression] condition2 ELSE
.
.
Valn WHEN [ after time expression] conditionn ELSE
Val [ after time expression] [WHEN condition];
With-When-Select
conditional selection statement

WITH parameter SELECT

Output<= val1 WHEN condition1,
Val2 WHEN condition2,
.
.
.

UNAFFECTED WHEN OTHERS;