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Introduction
# Hierarchy of hardware components: Top to bottom
VLSI(Very Large-Scale Integration) -- Circuits comprising
significant pieces of functionality: p, c, FPGA,CPLDs and ASIC.
MSI (Medium -Scale Integration) Circuits which brings
smaller, yet complete, pieces of functionally : DMA, JPEG.
SSI(Small- Scale Integration) we have electrical signals used
to represent our data and control information: Gates, Buffers

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The Hardware side- Getting started
Exploring Embedded System
Core: is the central hardware
core components in any modern embedded
application, ex: p or c.
Core interacts with and utilizes the
Instruction remaining components of the system to
set
Architecture
implement the required application.
ISA : hardware interaction with other
are under control of IS.
RTL: Here data transfer, operations on
Register data, and control flow are described/
Transfer level specified using RTN.
PHE : data are coming into the system
from surrounding environment and
from the application.
Physical Hardware
and Environment
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The Core Level- 4 major functional block
Input: Data as well as other
Datapath kinds of signals come into the
and system from the external
control world through the input
block.
Output :It provides a means
to send data or other signals
back to outside world.
Input Output Memory: It serves as to hold
collections of program
instructions ( software or
firmware) and short-term
storage for input data, output
Memory data and intermediate results
of computations.

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 Data and Control (CPU): It coordinates the activities of the
system as well as performs computations and data manipulation
operations necessary to executing the application.

Busses: We move signals into, out of, or throughout the system

on paths called Busses.

Definitions
(1) Bits : In the digital world, signals are expressed as collections of
binary 0s and 1s the elements of such collections are called Bits
(2) Width: It is the capacity of Bus to carry the signal.

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 Typical Bus structure
Signals to Outside
Signals from
world
outside world
Control

Memory Input Output

Datapath

Address
Data
Control

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 The Microprocessor and Microcontroller

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 The Comparison

In a microprocessor-based system, the CPU

and the various I/O functions are packaged as
separate ICs.

In a microcontroller-based system many, if

not all, of the I/O functions are integrated
into the same package with the CPU.

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 The Microcomputer
The microcomputer is a complete computer system that
uses a microprocessor as its computational core.
The microcomputer will also utilize numerous other LSI
circuits to provide necessary peripherals functionality.
The complexity of microcomputers varies from
simple units that are implemented on the single chip along
with a small amount of on-chip memory and elementary
I/O System
to the complex that will augment the microprocessor with
a wide array of powerful peripheral support circuitry

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 The Digital Signal processor

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 The Digital Signal Processor

The DSP is typically used in conjunction with GPP to perform

specialized tasks such as image, speech, audio, or video processing.
Features:
o Real world analog signals are captured through ADC, processed and
returned through DAC.
o Major strength is its ability to perform basic arithmetic
computations such as multiply, add, and shift (MAC)at the rate of
millions of instructions per second.
o The DSP device is architected as a Harvard rather than the Von
Neumann machine and
o Incorporates multiple computational units, a large number of
registers, and wide high-bandwidth data busses.

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 Notations:
LSB MSB
MSB LSB
0 31
31 0

Big endian Little endian

1 Word = 4 bytes = 32 bits

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 Address :

From the block diagram of microprocessor, we learnt that the

information is stored in memory.
Each location in memory has an associated address much like
an index in an array.
If an array has 16 locations to hold information, it will have 16
indices.

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 Instructions
Instruction : The purpose of an instruction is to direct the
hardware of the p to perform a series of actions.
Actions : These include: arithmetic, logical, assignment or read
the value of the variable, or move data from one place to another.
# Actions are called operations.
Operands: The entities that instructions operate on are denoted
as operands.
Arity: The number of operands that an instruction operates on
at any time is called the arity of the operation.
Example: y = x + z,
Action: addition,
Operands: x and z
Arity: 2 with addition.

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 Operators in C and C++: binary operators and unary operators.
Common C or C++ instructions
1. x = y; 2. z = x + y; 3. x = x + y; 4. ++x or x++;

Value of operand Adding two Adding two operands x & Increment the
y is assigned to operands x & y y and result is assigned value of the
operand x and result is to the operand x ,x acts variable. x is
assigned to the as dual role of source and both source
operand z destination. x initial value and destination
is lost.
Two operand or Three operands Two operands or two- One operand
two- address or three- address address instructions or one-
instruction instructions address
instruction

Operation: one Operation: Operation: Operation :

assignment addition and addition and addition
assignment assignment

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 Expressing Instruction
There are 3 classes of instructions: One, Two, or Three-
operand instruction.
If we have 32-bit word, it is divided into two fields
operand and operation.
Example :

operation Operand 0 One operand instruction

Source and destination

Operand 1 Operand 0 Two operand instruction

operation
Source/Destin source/Des

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 Register- A First Look

A register is a piece of short-term memory that temporarily holds

the operands during the execution of an instruction.

Depending on the Architecture of the microprocessor, they are

called CISC and RISC.
CISC- Complex Instruction Set Computers and
RISC- Reduced Instruction Set Computers
Here in above architectures, the number of Registers is not only
difference , their effect on system performance can be
significant.

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Bit assignment in 32-bit word of Microprocessor
System (Big endian)
MSB LSB
31 24 23 0

operation Operand 0

31 24 23 12 11 0

operation Operand 1 Operand 0

31 24 23 16 15 8 7 0

operation Operand 2 Operand 1 Operand 0

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Possible Interpretation of Set of Bits as Big Endian
representation
LSB
MSB
Unsigned Integer
31 24 23 0

+/- Signed Integer

31 24 23 12 11 0

+/- exponent mantissa Float

31 24 23 16 15 8 7 0

Char 3 Char 2 Char 1 Char 0 Character

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Embedded Systems- An Instruction Set View
Basics:
Assembly language: written using pseudocode and register.
Machine Language : collection of 0 and 1 that control the
hardware components in the execution of instruction.
Instruction Set : A definite set of executable instructions in a
processor.
Instruction Set Architecture(ISA): A set that drives the architecture
and provide to the programmer the public interface for the
underlying hardware.
Assembler: Convert from ALP to machine language.

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 Instruction Set- Instruction Types

Data Transfer
Flow of Control
Arithmetic and Logic

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 Data Transfer Instruction
Data transfer instructions are responsible for moving data around inside
the processor as well as for bringing data in from the outside world or
sending data out.
Each such instruction must have 3 pieces of information:
(i) the data (ii) the location of data- the source (iii) and where the data is
to be sent the destination.
The source and destination can be one of the following:
A register
Memory
An Input or Output Port.
Example: LD destination, source ; source and destination can be either
register or memory
ST source, destination
MOVE destination, source
XCH destination, source
PUSH/POP
IN/OUT destination, source

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 Addressing Modes
The way in which operands are specified in an instruction is
called as an Addressing modes.
Commonly used addressing modes are:
(1) Immediate : STI , LDI/LOADI, MOVI
Advantages : memory access is reduced, Fetching the
instruction retrieves the operand that the same time.
MOVE #BH

MOVE B

MOVE OPER1, #BH

MOVE OPR1 B

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 (2) Direct and Indirect

Here we are working with operand addresses rather than operand

values.
In both the cases , the first level of address information is contained
in the instruction.
Example: MOVE *OPR1, *OPR0
MOVE **OPR1, **OPR0

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 MOVE *OPR1, *OPR0

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 MOVE **OPR1, **OPR0

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 (3) Register Direct and Register Indirect:

The destination between the register direct and

register indirect modes lies in the content of the
referenced register.

Example: MOVE R2, R3 ; Register direct

MOVE R2, *R3; Register indirect

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 (3)Register Direct and Register Indirect

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 (4) Indexed Mode :
The indexed or displacement mode provides support for
accessing container-type data structures such as arrays
The Effective Address = [Base address + the contents of
indexing register]

Example : MOVE R3, R2[R1]; R2 base register(holds the

starting address of the
container
R1 index register or offset
value
Effective Address= R2 value + R1 value = 0 + 3 = 3 address
in container

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 (4) Indexed Mode

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 (5) Program Counter Relative Address:

(5) Program Counter Relative Address: It is mechanically

almost identical to indexed addressing mode,
Effective address= Value in program counter( Base Address) +
operand value (index register)
Example : ADD PC, [OPR0] ; OPR0=5, PC=2000,EA= 5+2000=2005

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 Execution Flow
The execution flow or control flow captures the order of
evaluation of each instruction.
We identify these as:
Sequential flow
Branch
Loop
Procedure or Function Call

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 (1)Sequential Flow
Each instruction contained in the program is executed in
sequence, one after another.
A significant amount of total code in an application is evaluated
and executed in sequential order.

initial

a= 10;
b= 20; MOVE R1, #AH; R1=A
MOVE R2, #14H; R2=14
c= a+b
ADD R3,R1,R2; R3=R1+R2
Final
C/C++ Sequential Flow Assembler Sequential Flow
Sequential Flow

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 (2) Branch
A branching construct terminates a sequential flow of control with a
decision point.
At such a point, one of the several alternative paths for continued
execution is taken based on the outcome of test on some condition.
Branch construct is used to implement an if else, switch, or case
statement.

# Typical Conditional codes

E,NE
Decision Z,NZ
Point GT,GE
LT,LE
V-OVERFLOW
C, NC
N-NEGATIVE

The Branch
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 C/C++ branch construct
if else construct:
if (a == b)
c= d+e;
else
c=d-e;
In the above C code fragment, the two variables are compared. If they are
equal, one arithmetic operation if performed; otherwise a second one is
executed.
Assembler if-else construct: CMP R2,R1
BE LABEL 1
SUB R3,R4,R5
BR LABEL2
LABEL 1 : ADD R3,R4,R5
LABEL 2: .
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 (3) Loop
The looping construct : do, repeat ,while or for statement.

Entry While (myVar< 10) L1: CMP R2,#AH;

Decision/ { BGE L2
condition index = index + 2; ADD R3,#2H
point myVar++; ADD R2, #1H
} BR L1
code L2: ..
..
Exit .
Decision C/ C++ Looping
point construct Assembler Looping
construct

The loop construct permits the designer to repeatedly execute a set of

instructions either forever or until some condition is met.

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 (4) Procedure or Function call
The procedure or function invocation is the most complex of the flow
of control constructs.
Such an invocation requires that the control flow leave the current
context, execute a set of instructions, and then return to the original
context.

CALL operand; PC is unconditionally saved

and replaced by specified
operand, control is transferred
Code i to specified memory location.
Function Call RET ; previously saved contents of PC
Code i+1 Function
are restored, and control is
returned to previous context.

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 Context switching is done using Stack
Stack is a data structure that occupies an area in memory.

TOP
3000 Code
SP
3 3053 CALL F1(3) ; return address and parameters
are pushed into stack, PC=5000
3054 3054 pop R2
3055 More Code

5000 code // Function Body
5053 Return ; pop the parameter and return
address, PC=3054

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 An ALU Block Diagram
X Y

Register Register

Arithmetic Logic Shifter

Multiplexer
State
Op-code
Machine

Register

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 Embedded Systems- A Register View
The Data path is collection of
Control signals registers and an associated set
Control Output micro operations on the data held
in the register.
Control The Control Unit directs the
ordered execution of the micro-
operations so as to effect the desired
Control Status transformations of the data.
Signals Information
Thus, the systems behavior
(execution of the ISA level
instructions) can be expressed by
Data input Data path Data Output
the movement of data among
those register, by operations and
transformation performed on
A Control and Data path the registers contents.
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 The Basic Register
A Register is storage device that is capable of holding the collection of
one or more bits.
D0 D0 D0 D0
D0
0
Dn-1
____ Dn-1
Dn-1 ____ Dn-1
Dn-1 write write
n-1
> >
____ ____
read read
____
enable

The Register at several Levels of Abstraction- Parallel Data Entry

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The Register at several Levels of Abstraction- Serial Data
Entry

Data
Data Data
____
____
write
write >
>
____
____ read
read ______
enable

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 Register Transfer Language
At the register transfer level, data transfer, operations on data, and control
flow are described/specified using a Register transfer language.
Within the language, individual operations and transfer are expressed using
register transfer notation(RTN).
Such a notation has a direct equivalent in contemporary hardware description
language(HDL) such as Verilog or VHDL, thereby facilitating the
transformation from design to implementation.
Example :
(1) Transfer from right to left
(2) If - then operation
(3) [index] select word from the memory
(4) < index > select bit or bits from register at index or range
(5) i..j Index range
(6) : = Text substitution
(7) # concatenation
(8) @ replication

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 Register view of Microprocessor
Type Instruction ISA level Register Transfer level
Data transfer Move Register MOVE R1, R2 R1 R2
Move from mem MOVE R1,memadx R1 (memadx)
Control Flow Unconditional BR $1 PC $1
branch
Conditional BNE $1 Con(PC $1)
branch If (cond) PC= $1
Logic AND register AND R1, R2 R1 R1 ^ R2
Shift register SHL R1, #3 R1<31..0> R1 <31-n0>
Arithmetic ADD register with ADDC R1, R2 R1 R1 + R2 +C
carry
Clear carry CLRC C 0
Program Dont execute an NOP PC (PC+1)
Control instruction
Stop executing HALT PC PC
instruction
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 RTN Model for Microprocessor
Data path and Memory Interface

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 Processor Control

The control of the

microprocessor datapath
Fetch
comprises 4 fundamental
operations defined as the
Instruction Cycle.
Fetch Decode
Decode
Execute
Next
Execute

Next

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 Execution Steps in detail
(1) Fetch: MOVE IR, *PC ; MAR PC , MDR Memory[MAR], IR MDR

(2) Decode: here opcode is decoded by Instruction decoder (ID) and

information is forwarded to the control logic, which will initiate the execute
portion of the instruction cycle.

(3) Execute: based the information by ID , the control logic performs the
sequence of steps necessary to execute the instruction.
Example : Store the contents of register in the named location in memory
Add the contents of register to a piece of data stored in memory

(4) Next: Compute the address the next instruction .

ADD PC, offset; TRO IR < n..m>, TR1 TRO + PC, PC TR1

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