15 October 2017 1

Outlines
Introduction
Why Junctionless Transistor?
Advantages of Junctionless
Transistor
Dopingless Transistors
References

15 October 2017 2
Introduction
Generally, most of the transistor are based on PN junction
or hetro junctions or schottky junctions.
The junctionless field effect transistor (JLFET) don't have
any PN or N+N or P+P junctions.
The device is basically a resistor in which the mobile
carrier density can be modulated by the gate.

15 October 2017 3
Introduction
Doping concentration is constant and uniform
throughout the device and typically ranges from 1019
and 1020 cm-3.
It has an ultrathin device layer of a highly doped
semiconductor, which is volume depleted in the OFF
state (at zero gate bias).
The device features bulk conduction instead of surface
channel conduction.

15 October 2017 4
Why Junctionless?
Realizing metallurgical junctions beyond 32-nm
node for a MOSFET has become extremely
challenging due to the need of ultrasteep doping
profiles.
Advantageous of Junctionless Transistor in
terms of Fabrication:
1) The simpler fabrication process.
2) Reduced thermal budget.
3) Easier to fabricate shorter channel length.

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Why Junctionless?
The down-scaling is effective way for achieving the
high-performance logic CMOS operation with low power.

The major drawback of downscaling of MOSFET is

tremendous increase in active or static power dissipation.

Increase in off-leakage current (Vg= 0 V)

Ref: H. Iwai et. al. Roadmap for 22 nm and beyond, Microelectronic Engineering, Volume 86,
Issues 79, JulySeptember 2009, Pages 1520-1528.
15 October 2017 6
Threshold Voltage Variability in JLT

[3] Sung-Jin Choi, Dong-Il Moon, Sungho Kim, Juan P. Duarte, and Yang-Kyu
Choi Sensitivity of Threshold Voltage to Nanowire Width Variation in
JLTransistors IEEE Trans. Electron Devices, vol. 32, no. 2, Feb. 2011.

15 October 2017
Advantage of Junctionless Transistor
Full CMOS functionality

Effective channel length (Leff) is larger than IM

A near-idealsubthreshold slope, close to 60

mV/dec at room temperature.

Reduced electric-field perpendicular to the

channel at ON-state reduces drain induced
barrier lowering (DIBL).

Less degradation of mobility than classical

transistors.
15 October 2017 8
Working of JLT

15 October 2017
Working of JLT

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Device Parameter of IM and JL DGFET
Inversion Mode Junctionless
Parameters
DGFET DGFET
Silicon film thickness (TSi) 12 nm 12 nm
Oxide thickness (Tox) 1.2 nm 1.2 nm
Effective Channel Length 18 nm
18 nm
(Leff) (L=45nm)
Width (W) 1 m 1 m
Source/Drain Extension 18 nm 18 nm
Channel Doping 1015 /cm3 1019 /cm3
Source/Drain Doping 1020 /cm3 1020 /cm3
N: 4.8 eV N: 5.25 eV
Metal work function for Gate
P: 4.6 eV P: 4.17 eV
N: 48 -m N: 79 -m
S/D Contact Resistance
P: 110 -m P: 79 -m
S/D Extension Contact N: 77 -m N: 46 -m
Resistance P: 46 -m P: 77 -m
N: 125 -m N: 125 -m
S/D Total Resistance
15 October -m
P: 156 2017 P: 156-m 11
 Performance metrics comparison
between IM and JL -DGFET

Ion/ Ioff DIBL SS

Device
(mV/V) (mv/dec)
nJL 7.0x105 44.7 68.13
nIM 0.5x105 101.3 79
pJL 9.0x105 43.2 67.4
pIM 1.0x105 100.2 78.2

Recognized in : Sahu, C.; Singh, J, Device and circuit performance analysis of double
gate junctionless transistors at L g = 18 nm, IET, The Journal of Engineering, Vol-1 pp1-
6, Apr 2014.
15 October 2017 9
Challenges in JLTs
1) Threshold Voltage Variability due to
Random dopant fluctuation and process
induced parameter variations
2) High OFF Current due to Band to Band
Tunneling at OFF state
3) Low ON-state current due to incomplete
ionization below room temperature
4) Low ON state current due to high
source/drain (S/D) series resistance and
poor mobility
5) Poor switch-off capability
15 October 2017 10
Threshold Voltage Variability in JLFET

JLFET suffers from large threshold voltage variability with silicon

body width as compared to inversion-mode devices.
Sung-Jin Choi, Dong-Il Moon, Sungho Kim, Juan P. Duarte, and Yang-Kyu Choi Sensitivity of
Threshold\ Voltage to Nanowire Width Variation in JLTransistors IEEE Trans. Electron Devices, vol. 32,
no. 2, Feb. 2011.
15 October 2017 11
Variability due to Random Dopant Fluctuations

Standard deviations of extracted parameters in JLFETs

due to RDF versus fin height and technology node
Leung, G.; Chi On Chui, Variability Impact of Random Dopant Fluctuation on Nanoscale Junctionless
FinFETs, Electron Device Letters, IEEE , vol.33, no.6, pp.767,769, June 2012.
15 October 2017
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Band to Band Tunneling in JLFET

As doping of the sourcechanneldrain regions of JLFET is high, the band

overlap during OFF state triggers tunneling of electrons from the valence band of
the channel to the conduction band of the drain.
OFF-state current computed by taking BTBT into account is several orders
higher compared with the OFF-state current when the BTBT model is absent.
S. Gundapaneni, et. al Effect of band-to-band tunneling on junctionless transistors, IEEE Trans. Electron
Dev., vol. 59, no. 4, pp. 10231029, Mar. 2012. 15 October 2017
16
How to address these JLTs issues?

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Doping-less DGFET
A distinctive approach of implementing a junctionless
transistor (JLT) without doping (doping-less) the
ultrathin silicon film is proposed for the first time.

The charge-plasma concept is employed to induce N+

layer in source and drain for a n-channel JLT using
appropriate metal workfunction electrodes.

Recognized in: Sahu, C.; Singh, J., "Charge-Plasma Based Process Variation Immune Junctionless Transistor,"
Electron Device Letters, IEEE , vol.35, no.3, pp.411,413, March 2014.
15 October 2017 18
How we reached to new design?

Charge plasma p-n diode [2] Charge plasma BCPT [3]

R.J.E. Hueting, B. Rajasekharan, C. Salm and J. Schmitz, Charge Plasma P-N Diode, IEEE Electron Device
Lett., vol.29, no.12, pp.1367-1368, Dec. 2008.
M. J. Kumar and K. Nadda, Bipolar Charge Plasma Transistor: A Novel Three Terminal Device, IEEE Trans..
Electron Devices, vol.59, no.4, pp.962-967, April 2012.
15 October 2017 19
Doping-less DGFET Working

OFF state (No bias) ON State (Vgs=1V, Vds=0.1V

Electron Concentration distribution to show OFF and

ON state via TCAD simulation.

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Band Diagram and Electron/Hole Profile

15 October 2017 21
Advantages of doping-less FET
1) Free from RDFs due to undoped silicon body
throughout from source to drain
2) Smaller sensitivity towards parameter
variations
3) Higher ON current due to higher electron-
mobility product
4) Lower OFF current due to reduction in band
to band tunneling
5) Lower SCEs due to larger Leff

15 October 2017
22
Device simulation parameters
Doping-less Junctionless
Parameters
DGFET DGFET
Silicon film
10 nm 10 nm
thickness (TSi)
Effective oxide
1 nm 1 nm
thickness (EOT)
Gate Length (Lg) 20 nm 20 nm
Width (W) 1 m 1 m
DL-DGFET
Source/Drain
10 nm 10 nm
Extension
Metal work
function/doping 3.9eV(Hafnium) 1019 /cm3
for Source/Drain
Metal work 5.25eV(P+
4.66eV(TiN)
function for Gate poly)
JL-DGFET
Doping 1015 /cm3 1019 /cm3
15 October 2017 23
Methodology of Device Simulation
Mobility Models
CONMOB : low eld mobility related to doping density
FLDMOB: high eld velocity saturation depending on
parallel electric eld in the direction of current ow.
Recombination models for minority carrier recombination
SRH
Method
Gummels method (or the decoupled method), along with
Newtons method (or the fully coupled method) is used to
solve the equations involved in conventional drift-diusion
model.

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Transfer Characteristics Calibration

M. Vinet et al., Bonded planar double-metal-gate NMOS transistors down to 10 nm, Electron Device
Letters, IEEE , vol.26, no.5, pp.317,319, May 2005.
15 October 2017 24
Results and Discussion

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Lower Threshold Voltage Variability

In, JL-DGFET 10% variation in Tsi = 10 nm at doping level of Nd = 2x1019 cm-3 ,

yield approx. 200 mV/nm change in Vth, which was also validated analytically
using a model proposed in [4].
Recognized in : Sahu, C.; Singh, J., Potential Benets and Sensitivity Analysis of Dopingless Transistor
for Low Power Applications, IEEE, Transaction on Electron Devices, Jan. 2015 (In Press).
15 October 2017 27
Effect of doping variation

Effect of doping for conventional (a), (c) and doping-less JLT (b)
and (d) with variation in Tsi and Nd, respectively at Vds=0.9V.
Recognized in: Sahu, C.; Singh, J., "Charge-Plasma Based Process Variation Immune Junctionless Transistor,"
Electron Device Letters, IEEE , vol.35, no.3, pp.411,413, March 2014.
15 October 2017
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Effect of Scaling Gate Length

Effect of Gate Length scaling on different performance

parameters
Vth roll-off and SCEs are less in DL-DGFET than JL-
DGFET. 15 October 2017
29
Longer Effective Channel Length

DL-DGFET consist a longer effective channel length (Leff ) than JL-

DGFET. This increase in Leff reduce SCEs of DL-DGFET and makes
it further scalable.
Recognized in : Sahu, C.; Singh, J., Potential Benets and Sensitivity Analysis of Dopingless Transistor
for Low Power Applications, IEEE, Transaction on Electron Devices, Jan. 2015 (In Press).
15 October 2017
30
Performance Parameter Comparison between IM
and JL and DL-DGFET

Ion/ Ioff DIBL SS

Device
(mV/V) (mv/dec)
nDL 9.0x105 34.7 63.13
nJL 7.0x105 44.7 68.13
nIM 0.5x105 101.3 79
pDL 1.1x106 32.7 64.2
pJL 9.0x105 43.2 67.4
pIM 1.0x105 100.2 78.2

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Effect Scaling Si Thickness

Effect of Si thickness scaling on different performance

metrics
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Effect of Scaling Spacer

Effect of spacer length scaling on different performance

metrics
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Effect of Scaling EOT

Effect of EOT scaling on different performance metrics

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BTBT reduction in DL-DGFET

BTBT comparison between JL and BTBT comparison between JL and

DL-DGFET at different Si Thickness DL-DGFET at different doping

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Incomplete ionization in DL-DGFET

Transfer characteristics with and ON current at different

w/o incomplete ionization temperature

Recognized in : Sahu, C.; Singh, J., Potential Benets and Sensitivity Analysis of Dopingless Transistor
for Low Power Applications, IEEE, Transaction on Electron Devices, Jan. 2015 (In Press).
15 October 2017
36
Effect of Parametric Variation

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Effect of S/D oxide thickness

Smaller oxide thickness

(S/D side) increases
electric field between metal
and semiconductor
(Vertically), hence, it
accumulate more no of
electrons in this area,
which leads to improved
ON current.

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38
Effect of interface traps

ON current reduces with

an increase in trap density
but it is still maintained
substantially upto traps
level of 10 11 cm-2

Recognized in : Sahu, C.; Singh, J., Potential Benets and Sensitivity Analysis of Dopingless Transistor
for Low Power Applications, IEEE, Transaction on Electron Devices, Jan. 2015 (In Press).
15 October 2017
39
Effect of Spacer Length

The degradation in ON
current of DL-DGFET with
spacer length is more severe
because of increased
external resistance (direct
consequence of lower doping
in underlap region).

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Effect of External Resistance
DL-DGFET has higher
REXT than JL-DGFET
because of the lightly
doped region under the
spacer.
Enhanced mobility of
carriers leads to lower
RCH that will
compensate effect of
REXT for Lg = 20 nm
and beyond.

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Sensitivity Analysis

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42
Sensitivity Analysis for 10% change in Device Parameters

IM
Parameters JL [9] IM[9] DL
underlap[9]
Intrinsic
16.2 500 26 15
delay (ps)
S (Lg) 2.31 10.56 2.7 1.5
S (Tox) 4.04 4.63 2.25 2.5
S (Tsi) 7.05 6.95 1.48 2.45
S (Nd) 4.41 0 0 0
S = (M/M)/(P/P)
M= Performance metrics ()
P=Parameters (Lg,Tox,Tsi, Nd )
[9] Parihar, M.S.; Ghosh, D.; Kranti, A, Ultra Low Power Junctionless MOSFETs for Subthreshold Logic
Applications, Electron Devices, IEEE Transactions on , vol.60, no.5, pp.1540,1546, May 2013.
15 October 2017
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Subthreshold Analog/RF
Performance Investigation

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Advantages of Subthreshold Operation
In recent years, the analog/RF market is increasingly
inclining toward CMOS technology for its extremely low
power applications and improved RF figure of merit (FOM)
due to effective downscaling of MOSFET devices .

The subthreshold operation of MOSFETs offers a wider scope

for analog applications due to higher intrinsic gain (Avo) and
higher transconductance generation factor(gm/Id ).

It is due to exponential
current-voltage
(I-V) characteristics
of the transistor.

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IM, JL and Proposed Structures

Double Gate (a) Underlap Inversion Mode (b) Junctionless (c) Doping-
less FETs 15 October 2017 46
Analog/RF Performance Metrics

Sahu, C., Kumar A., Singh, J., Analog/RF Performance Investigation of Doping-less DGFET for
Subthreshold ULP Applications, IEEE, Transaction on Electron Devices (Under Review).
15 October 2017
47
Continue

In JL-DGFET conduction channel is confined at the center of the channel,

whereas, for DL-DGFET the it is spread out across the silicon film i.e volume
accumulation and DL-DGFET shows higher nee product.

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Continue

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Proposed Fabrication of DL-DGFET

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50
Proposed Fabrication Process Flow

Proposed process flow for the fabrication of DL-DGFET structure. (a)

SOI substrate formation (b) Fin Formation (c) Gate formation (side
View) (d) Gate patterning (top view), Front View (e) oxidation (f)
selective etching for S/D electrodes (g) S/D contact formation and (h) final
structure of DL-DGFET.
Recognized as : Sahu, C.; Singh, J., Potential Benets and Sensitivity Analysis of Dopingless
Transistor for Low Power Applications, IEEE, Transaction on Electron Devices, Jan. 2015 (In
15 October 2017 51
Press).
6T SRAM Cell Simulation

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Methodology of Circuit Simulation

W / L MN 1 ,MN 2
CR 1
W / L MN 3 ,MN 4

W / L MP 1 ,MP 2
PR 1
W / L MN 3 ,MN 4
Recognized as : Sahu, C.; Singh, J, Device and circuit performance analysis of double gate
junctionless transistors at L g = 18 nm, IET, The Journal of Engineering, Vol-1 pp1-6, Apr 2014.
15 October 2017
53
6T-SRAM Cell Simulation results

Recognized as : Sahu, C.; Singh, J., Potential Benets and Sensitivity Analysis of Dopingless Transistor
for Low Power Applications, IEEE, Transaction on Electron Devices, Jan. 2015 (In Press).
15 October 2017
54
 PD/FD SOI Devices
Planar Fully Depleted Silicon on Insulator (FD-SOI) technology relies on an ultra-thin layer of
silicon over a Buried Oxide (commonly called BOx). Transistors built into this top silicon layer
are Ultra-Thin Body devices and have unique, extremely attractive characteristics. Two flavors of
buried oxide can be used: standard thickness (typically 145nm thick as classically in volume
production PD-SOI digital chips today), or ultra-thin BOx, for example 10 or 25nm (UTBOx,
Ultra-Thin Oxide).
From a physical point of view, the very
thin silicon layer enables the silicon
under the transistor gate (the body of
the transistor) to be fully depleted of
charges. The net effect is that the gate
can now very tightly control the full
volume of the transistor body. That
makes it much better behaved than a
Bulk CMOS transistor, especially as
supply voltage (hence gate voltage)
gets lower and transistor dimensions
shrink. In addition, FD-SOI does not
require doping in the channel.
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 Why PD/FD SOI?
FD-SOI offers less process complexity, scaling, leakage and variability issues to
further shrink CMOS technology beyond 28nm. Following major benefits are:
excellent electrostatic control of the transistor, intrinsic to FD-SOI, acts as a
performance booster and enables lower VDD (therefore lower power consumption)
whilst reaching remarkable performance,
FD-SOI strongly reduces the random dopant fluctuation, thus drastically cutting
transistor threshold (VT) variability. In particular, this enables stable, dense, and high-
yielding SRAM, functional at very low VDDmin (even in near- or sub-threshold mode
with a good SNM),
Simulations and early silicon data predict that, at 22nm node, 6T SRAM macros on FD-SOI
could reach 6-sigma yield at VDD as low as 0.5-0.6V [C Shin et al., UCB, SOI
Conference 2009 K Cheng et al., IBM, IEDM 2009]
FD-SOI is intrinsically Low Leakage and regains good control of Short Channel
Effects.
One consequence is the ability to aggressively shrink the gate length, making it easier
to fit devices into smaller and smaller pitches, therefore increase logic density to
continue Moores law.

15 October 2017 56/59

FinFET and FD-SOI devices

15 October 2017 57/59

Bulk and FD FinFET devices

15 October 2017 58/59

 SOI Disadvantages
Floating body causes the History Effect
Body voltage depends on if device has been idle or switching
This changes Vt, which changes the delay of the circuit
Circuit delay changes with its history of switching activity!
Matches matching transistors for analog designs difficult because
even if transistors are next to each other, can have different
characteristics because of changing VT
Self-heating
The oxide is good thermal insulator as well as electrical insulator
Heat accumulates in switching transistors rather than spreading
throughout the substrate, slow them down.
A problem for large transistors that switch fast, i.e, clock buffer
transistors.
15 October 2017 61/59
Alpha Particles

Sources
Cosmic Rays (aircraft electronics vulnerable)
Decaying uranium and thorium impurities in
integrated circuit interconnect
Generates electron-hole pairs in substrate
Excess carriers collected by diffusion terminals
of transistors
Can cause upset of state nodes floating nodes,
DRAM cells most vulnerable
Radiation Effects in SOI Technologies
In bulk MOS transistor, only very top region (0.1- 0.2 um
thick) of the silicon wafer is used for carrier transport. The
inactive volume, more than 99.9% of the wafer, is used as a
mechanical support of the active device. Unfortunately, the
inactive volume can induce undesirable effects, for example
leakage currents, which cannot be modulated by the gate.
SOI is a key factor for excellent performance of the IC in
radiation prone environments.
Performance and reliability are significantly increased by
incorporating a silicon dioxide layer to isolate the transistors
from the substrate.
Developed for radiation-hardened military and space
applications.
Full dielectric isolation of individual transistors, which
prevents latchup.
J. R. Schwank, et al, Radiation Effects in SOI Technologies, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 50, NO. 3, JUNE 2003
Radiation Effects in SOI Technologies
Reduce Parasitics - Isolation from the bulk silicon
substrate reduces capacitive loading which delivers high
speed performance and lower power consumption.
Low Noise and Crosstalk - SOI CMOS enables novel
process and design techniques to achieve a very low
noise operation and 4-6 dB lower cross-talk to support
high performance mixed mode circuits.
No Latchup - SOI inherently eliminates latchup, which
can occur in CMOS devices due to a parasitic condition
in which at least one PNP and at least one NPN
transistor act like a silicon controlled rectifier (SCR). This
parasitic PNP structure creates a low-impedance path
between the power rails and can permanently damage
the device.

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 Parasitic Structures
Equivalent
Bipolar
Transistor

Fully depleted transistors partially depleted transistors
The parasitic bipolar transistor:
the floating body node is the base of
the parasitic bipolar transistor. It can
be triggered by specific electrical
conditions (high-drain voltage),
radiation, or electrical charges that
forward bias the body-source diode.
To avoid its onset, the body region can
be tied to the source potential or
ground.
back-gate
Transistor
equivalent electrical structure
The parasitic back-gate transistor: The back
side of the wafer is the gate of the back-gate
transistor, and the thick BOx acts as the gate
insulator. It is triggered mainly under total dose
irradiation, because of trapped charge in the BOx.
When the back-gate transistor is conducting, an
inversion layer appears in the top silicon film near its
interface with the Box. A simple method for
quantifying the amount of radiation-induced charge
buildup in the buried oxide is to measure the Vt of
the back-gate transistor.