RTL VERIFICATION AND ASIC

IMPLEMENTATION OF M25P40 FLASH

MEMORY
Mark Vincent F. Abadies
Ahmad Maher S. Lucman
 STATEMENT OF THE PROBLEM

This study aims to provide a thorough understanding

and analysis of a low power flash memory IP and test
its functionality and compatibility with the
openMSP430 microcontroller via RTL synthesis using
Verilog. This also aims to provide a low power
implementation of the flash memory IP using the tools
from Synopsys.
 OBJECTIVES

To provide an understanding of the design architecture of a flash memory IP to

be compatible with the openMSP430 microcontroller core.
To implement and verify the functionality of the RTL code.
To provide a complete ASIC flow of the project.
To provide a low power implementation of the flash memory architecture.
 M25P40

The M25P40 is an 4Mb (512Kb x 8) serial Flash memory device with advanced
write protection mechanisms accessed by a high-speed SPI-compatible bus. The
device supports high-performance commands for clock frequency up to
75MHz. The memory can be programmed 1 to 256 bytes at a time using the
PAGE PROGRAM command. It is organized as 8 sectors, each containing 256
pages. Each page is 256 bytes wide. The entire memory can be erased using the
BULK ERASE command, or it can be erased one sector at a time using the
SECTOR ERASE command.
 CHALLENGES:

RTL code of M25P40 is provided as is by the manufacturer and is hard to

modify.
The architecture is quite complex.
 CHALLENGES

Not enough reference for RTL Verification for flash memories.

Complexity.
No novelty or innovation

 MODELING THE PHYSIC AL

CHARACTERISTICS
OF NAND FLASH MEMORY

The first tool, called FlashPower, is a microarchitecture level modeling tool that provides
a detailed analytical power model for Single-Level Cell (SLC) based NAND flash
memory. FlashPower estimates the power consumed by a NAND flash memory chip
during its various operating modes.

The second tool, called Flash EnduraNCE (FENCE), models the endurance
characteristics of NAND flash and captures the impact of stress and recovery on
NAND flash memory cells. Using FENCE, we show that the recovery process, which
prior studies on flash based SSDs have not considered, significantly boosts endurance.
Using a set of real enterprise workloads, we show that this recovery process allows for
orders of magnitude higher endurance than those given in datasheets.
DYNAMIC NOR DECODER FOR 5T
SINGLE POLY FLASH MEMORY

Mark Vincent F. Abadies

Ahmad Maher S. Lucman
 2 to 4 NAND Decoder 2 to 4 NOR Decoder

Dynamic logic implementation for the Dynamic logic implementation for the
NAND gate and inverter NOR gate
NAND gate NOR gate

inherent high-speed of dynamic logic -The total resistance encountered during the
evaluate phase does not increase and the NOR
As larger decoders are desired, the number of
decoder resolves more quickly than NAND.
fan-ins on each NAND gate also increases.
- During the precharge phase, PMOS transistor is
More NMOS transistors are added to the stack,
conducting and the decode output line is
the resistance of the pull down path increases.
precharged to logic high level thus all the decode
As transistors are added to the stack, the size of output are high. Thereby, violating the one-hot-
the transistors increases to reduce the resistance decode condition.
of each individual transistor while keeping overall
resistance constant.
Larger transistor consume more space and lead
to larger input capacitances which slows the
circuits response.
Additional transistor has voltage drop across it
and so the top transistors have increasingly
higher source voltages during switching and
correspondingly deteriorated switching
performance.
DYNAMIC NOR GATE DECODER WITH
CROSS-COUPLED OUTPUT
3-8 ROW DECODER AND 4-16 COLUMN
DECODER
5T SINGLE POLY FLASH MEMORY
 PMOS transistors are utilized to for M1 and M2 to achieve high speed programming by
biasing the devices in non-depletion mode.

Tight bitline pitch.

During the program operation, a high voltage is applied to the cells to be programmed
while self-boosting inhibits program in unselected bitlines by turning off pass transistors
S1 and S2.
M2 (erase device) along with self-boosting technique allows column peripheral circuits to
be built using low voltage core devices which improves operating speeds and reduced
power consumption.