Lecture 8

Instruction Sets
Part II: Data Types & Addressing Modes

Zelalem Birhanu, AAiT 1

 In this lecture:

Data Types
Addressing Modes

Zelalem Birhanu, AAiT 2

 Data Types

Types of data that can be processed by instructions

Can be categorized as:

Numeric
Integers (signed or signed), floating-point, BCD

Nonnumeric
Characters (ASCII, UNICODE), Boolean (logical) data

Zelalem Birhanu, AAiT 3

 X86 Data Types

Integer
Byte unsigned(signed) integer (8 bits)
Word unsigned(signed) integer (16 bits)
Double word unsigned(signed) integer (32 bits)
Quad word unsigned(signed) integer (64 bits)
Signed integer uses 2s complement representation

Floating-point (IEEE 754 representation)

Single precision (32 bits)
Double precision (64 bits)
Double extended precision (128 bits)

Others
Bit field, Bit string, BCD
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 Addressing Modes

Consider the following instruction format

Operation Code Addresses

(Opcode) (operands)

The addresses (operands) field may reference (specify) memory

location, register or an immediate value

Addressing Modes
How is the address of an operand specified?

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 Addressing Modescntd

Common addressing modes

Immediate
Direct
Register
Register indirect
Displacement
Stack

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 Immediate Addressing

Operand is specified in the instruction itself

e.g. MOV R1,100 (R1100)

Immediate
operand
Advantage
Does not require extra memory reference to fetch the operand

Drawback
Only a constant can be supplied
The number of values is limited by the size of the operand
field (e.g. 0 to 255 if the field is 8 bits)

Zelalem Birhanu, AAiT 7

 Direct Addressing

Full memory address is specified in the address field of the

instruction

CPU Memory
e.g. MOV R1,[100] R1 96 99 78

Memory 100 96
Address 101 0
Advantage
Requires only one memory reference

Drawback
Can address a limited number of memory locations (relatively
smaller address space) (e.g. If the field is 8 bits the instruction can
only access 256 memory locations)
Zelalem Birhanu, AAiT 8
 Register Addressing

Register address is specified in the address field of the

instruction

e.g. MOV R1,100 (R1100)

Register
Address

Most common addressing mode in most computers

Q. If a CPU has 32 registers, how many bits are required for

register address field of an instruction? Ans: 5

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 Register Indirect Addressing

Register that holds memory address is specified in the

address field of the instruction

CPU Memory
e.g. MOV R1,[R2] R1 0 99 78
R2 101 100 96
Memory
Address 101 0
Advantage
Can address larger number of memory locations compared
with direct addressing

Q. If a CPU has 32 registers (16 bits each), how many memory

locations can be addressed using register indirect addressing?
Ans: 216
Zelalem Birhanu, AAiT 10
 Displacement Addressing
Combines direct addressing and register indirect addressing

Main memory address is added with a displacement value to

get the effective address in memory

e.g. MOV R1,[R2+100] CPU Memory

R1 55 109 36
displacement 110 55
R2 10
value
111 0
Effective address =
R2+100=10+100=
110
Typical application is to access arrays using the displacement
as a pointer to the start of the array and the register value as an
array index
Zelalem Birhanu, AAiT 11
 Displacement Addressingcntd

e.g. Assume we have an array of four elements. Let the memory address
of the first element is 100. A program that adds 1 to every element of the
array is given below:
MOV R1,4
Memory Memory
MOV R2,0
(100+0) 100 52 100 53
loop:
(100+1) 101 55 101 56
INC [R2+100]
(100+2) 102 0 102 1
INC R2 103 94
(100+3) 103 93
DEC R1 104 23 104 23
JNZ loop

Q. What other addressing modes are used in the above program?

Zelalem Birhanu, AAiT 12
 Displacement Addressingcntd

Known by a variety of names:

PC- relative addressing: Address field of instruction contains

displacement value (PC register is specified implicitly)
EA = PC +address field (displacement value)
Base-register addressing: Address field of instruction
contains displacement value
e.g. MOV R1, [R2+100]
displacement value
Indexed addressing: A referenced register contains
displacement value
e.g. MOV R1, [R2+100]

displacement value 13
 Stack Addressing

An implied addressing that refers to the top of a stack

It is implied that the address is contained in side a stack

pointer register

CPU Stack
e.g. PUSH R1 R1 0 201 0
200 23
SP 201
199 15
Stack
pointer
Register

Zelalem Birhanu, AAiT 14

 X86 addressing modes

Register, Immediate
e.g. MOV AX, 0546
Direct
e.g. ADD AX, [0546]
Register Indirect
e.g. MOV [BX],AX
Displacement
Indexed
e.g. MOV AX, [R+0645] where R is an Index register (SI or DI)
Based
e.g. MOV AX, [R+0645] where R is a base register (BX or BP)

Zelalem Birhanu, AAiT 15

 More Readings

1. Computer Architecture and Organization,

William Stallings, 8th edition (chapters 10&11)

1. Structured Computer Organization, Andrew S.

Tanenbaum, 5th edition (section 5.2&5.4)

Zelalem Birhanu, AAiT 16