Assembler Training (Basics) Part - 1

Assembler Training (Basics)
Part -1
Assembler Training
• What is ASSEMBLY Language?

– Low Level Programming Language
– Symbolic forms of Language
– Represents a single machine instruction
– Machine dependent
– Difficult to use than the High-Level Language
Assembler Training
• Advantages over high-level language

– Provides complete access to the instruction set of
a computer
– Memory and time efficient codes can be
developed
– Learning assembler language helps in
understanding computer concepts
Assembler Training
• Disadvantages
– Application Development time is more.
– Applications are machine dependent.
– Difficult to learn and understand
– Does not provide data structure facilities like in
high-level language
Assembler Training
• Advantages over machine language

– Use of mnemonic opcodes helps in
remembering the instructions.
– Symbols can be used
– Macros can be used to generate repeated codes
– Conditional assembly enables to tailor the code
generated
Assembler Training
IBM -370 /XA BASIC MACHINE

ARCHITECTURE
A. Main Storage
B. Central Processing Unit (CPU)
C. Input/Output system
Assembler Training
Main Storage
• Addressed by 24 bits or 31 bits
• Contains program and data
• Byte is the least addressable area
• Bytes can be addressed in groups (2,4 or 8)
• Instruction execution is faster if data is aligned in
fullword binary
Assembler Training
CPU
CPU executes five categories of instructions
– General instructions
– Decimal instructions
– Floating-point Instructions
– Control Instructions
– I/O Instructions
Assembler Training
CPU (Contd.)
CPU Contains
• Program Status Word (PSW)
• General Purpose registers (GPRs)
• Floating Point Registers( FPRs)
• Control Registers ( CRs)
• Arithmetic and Logical Unit (ALU)
• Interrupt handling logic
Assembler Training
CPU (Contd.)
• Program Status Word (PSW)

– 64 bits in length
– Contains the CPU status ,like result of an
arithmetic operation
– Contains the next instruction address
Assembler Training
CPU (Contd.)
• General Purpose Registers( GPR)
– 16 registers are available
– Each is 32 bits in length
– addressed by 0-15 of R field of the instructions
– Used as accumulators in binary arithmetic
instructions
– Two consecutive registers can be used to hold
64 bit operands and is addressed by even
register
Assembler Training
CPU (Contd.)
• Floating Point Registers
– Available for floating point operations
– 4 registers
– Each is 64 bits in length
– Addressed by 0,2,4,6
– Can contain short or long operand
– Two adjacent registers can be used as 128 bit
register
– Identified by R field of the instructions
Assembler Training
CPU (Contd.)
• Control Registers
– 16 control registers are available
– Each one is 32 bits in length
– Indicates facilities available in the system
– Addresses by 4 bit R filed of control
instructions
Assembler Training
Input/Output System
• Directs the flow of information between I/O derives and
main storage
• CPU is relieved of communicating directly to I/O
devices
• Data processing and I/O processing are concurrent
• Consists of channel subsystem ,control unit and
I/O
Assembler Training
Assembly Language Basics

Assembler Training
Assembly Language Basics
• Assembly statement format
• Types of instructions
• Instruction fundamentals
• Types of operands
• Types of assembler machine instructions
• Symbols
• Storage allocation
• Literals
• Other directives
Assembler Training
Assembly Language Basics(contd.)
• Assembly Statement Format
Name field Operation field Operand field Remarks field Sequence field
– Not Free format

– Blank lines are invalid
– Fields in statement are separated by blanks
– Name/Label field starts on column 1 and
maximum 8 characters in length
Assembler Training
• Assembly Statement Format (contd.)

– To continue a statement to next line , type a non
blank character in col. 72 and start next line at col.
16
– Maximum 3 lines of continuation are allowed.
– Comment character (‘*’) on column 1
Assembler Training
• Types of Instructions
Assembler supports three types of instructions

– Machine instructions
– Assembler instructions
– Macro instructions
Assembler Training
• Instructions Fundamentals
– Instructions are unsigned binary integer.
– 2,4 or 6 bytes in length.
– First byte normally contains the operation code.
– Operations code specifies the function of the
instruction.
– Operand designation follows the operation code.
Assembler Training
• Operands
– Entities that are involved in operations defined by
opcode.
– Operands can be specified either implicitly or
explicitly.
– Four types of operands
• Register operand
• Storage operand
• Implied operand
• Immediate operand
Assembler Training
• Operands(contd.)
Register Operand
• Identified by the R field
• Specifies either GPR or FPR
• Operand access is faster
Example
ADD1 AR 1,2
Assembler Training
Immediate Operand
– Contained with in the instruction itself
– Eight bit value
– Self-defining term or an absolute symbol can be used
Example
Clear NI PARM,B’10000000’
PARM DC X’12’
Assembler Training
Storage Operand
– Resides in memory
– Address is not specified explicitly
– Base and/or Index method is used
– Register 0 cannot be used as base or index register
– 12 bit displacement could be specified.
– BALR instruction is used to load base register
– If symbols are used assembler resolves it to base displacement
form.
Assembler Training
Address calculation
Address is calculated by specifying a base address and the
displacement from the base. An Index can also be specified in some
instructions.
Effective address =(b) +(x)+disp
Effective address =(b) +disp
Size of storage operand
– Single or group of bytes
– length is implied by the instruction or specified in the instruction
Example LPSW D2(B2)
Assembler Training

Implied Operand
• Instruction itself assumes the operand
Assembler Training
• Instructions Classification
Instructions are classified according to the types of
operands
RR Instructions :Both operands are in registers.
RS Instructions :First Operand is in the register and the
other in the storage.The address of the storage location is
specified in base displacement form.
RX Instructions: Similar to RS instructions ,but the storage
address is given by base,index and displacement form .
Assembler Training
S Instructions :First Operand is in the storage and the other
operand is the implied operand.
SI Instructions: First Operand is in the storage and the
second is the immediate operand.
SS Instructions: Both Operands are in storage.
Examples
1. RR type instruction
AR 1,2 reg1==reg1+reg2
Assembler Training
Examples (contd.)
2. RS type instruction
BXH 1,3,D2(B2) reg1==reg1+reg3
if reg1>reg3 then branch
3. RX type instruction
L 1,D2(X2+B2) reg1 <==(D2+X2+B)
4. S type instruction
LPSW D2(B2)
Assembler Training
Examples (contd.)
5.SI type instruction

NI D1(B1),I2
6.Storage type instructions
MVC D1(L0,B1),D2(B2)
PACK D1(L1,B1),D2(L2,B2)
MVCP D1(R1,B1),D2(B2,R3)
Assembler Training
• Symbols
– A sequence of one to eight letters and digits that
begin with a letter .Letters includes $ # @
– defined when they occur in the name field of an
instruction
– Absolute value assigned to a symbol by using
‘EQU’ assembler instruction with an absolute
value operand.
– A relocatable address value assigned to a symbol
by using it on name filed of a machine instruction.
Assembler Training
• Symbols(contd.)
Symbols can be used in the operand fields to
represent registers ,displacements ,length, immediate
data ,address etc.
Example
LABEL001 MVC S1,S2
BR EXIT
EXIT BR 14
S1 DS CL100
Assembler Training
• Symbols (contd.)
Advantages of Symbols
– Easier to remember and use
– Meaningful symbol names instead of values
– For address the assembler calculates the displacement
– Change the value at one place (through an EQU) instead of
several instructions
– Printed in the cross-reference table by the assembler and
hence easy to find in the program listing
Assembler Training
Self Defining Terms
– Constants written in decimal ,binary, hexadecimal , or
character form
– Can be used to designate registers,masks, and
displacement within the operand entry
– Decimal self-defining term
• An unsigned decimal integer
• Maximum number of digits 10
• Maximum value 2*31-1
Assembler Training
Self Defining Terms(contd.)
– Binary self defining term
• A binary integer within apostrophes and preceded by a
B
• Maximum number of digits 32
• Maximum value 2*31-1
– Hexadecimal Self-defining
• A hexadecimal integer within apostrophes and
preceded by a X
• Maximum number of digits 8 and Maximum value
2*31-1
Assembler Training
Self Defining Terms(contd.)

– Character Self-defining
• A character string within apostrophes and preceded by
aC
• Maximum number of characters 256
Assembler Training

Location Counter
– Assembler runs a location counter to assign addresses to
program statements
– Refer to the current value using ‘*’
– Incremental after assembling each instruction
Example:
LOOP EQU *
B * +8
Assembler Training
Attributes of symbols
– Length
– Type
Length Attribute
– Referred to as L’ symbol
– For a symbol defined by ‘DC’ or ‘DS’ , it is the implicit or
explicit length.
– For a symbol referring to a machine instruction , it is the
length of the instruction.
– For a ‘EQU’ symbol ,it is the length of the left most term
or supplied by the second operand.
Assembler Training
Length Attribute(cont.)
Example Length
A DS F 4
ARRAY DS 20FL(L’A) 4
B DS XL3 3
LOOP AR 1,2 2
AA EQU A+4 4
BUF EQU A,256 256
BUF1 EQU *+1 1
BUF3 EQU * , 80 80
Assembler Training
• Symbols(contd.)
Type Attribute
– Referred to as T’ symbol
– Gives the one character type code of the symbol
Data Alignment
– Instructions have to be aligned on half-word boundary
– Data can be specified to be aligned to
• Double -word (D, Divisible by 8)
• Full-Word (F, Divisible by 4)
• Half -Word (H, Divisible by 2)
Assembler Training
Data Alignment(contd.)
– Location counter skipped as per alignment requirement
EXAMPLE
0100 DC C’ABC’
0103 SKIPPED
0104 DC H’10’
0106 SKIPPED
0107 SKIPPED
0108 DC F’560’
Assembler Training
Assembly Language Basics(contd..)
• Storage allocation
Define Storage (DS)
– To reserve storage
– Storage contents are uninitialized
– Initial value is used for calculating the size of the storage
– Duplication factor can be specified
– Location counter advanced by the number of bytes
associated with the specified type and duplication factor
– Similar to variable declaration without initial values in a
higher level language
Assembler Training
• Storage allocation(contd.)
Define Storage (DS) ( contd.)
SYNTAX:
{NAME} DS {DUP} TYPE {MOD} {‘V1,V2,…..Vn’}
DUP - Duplication factor
MOD - Modifier
Example
FULLVAL DS F
HALFVAL DS H
NAME DS CL26
NAMEARAY DS 20CL26
TABLE DS 100H
Assembler Training
Define constant (DC)
– To Reserve storage and initialize it with values.
– Location counter advanced by the number of bytes
associated with the specified type.
– Not true constants,the values can be changed in the
program.
– Similar to specifying initial values invariable declarations
of a high level language.
Assembler Training
Define constant (DC)
SYNTAX:
{NAME} DC {DUP} TYPE {MOD} ‘V1{,V2,V3,..,VN’}
DUP-Duplication factor .
MOD-Modifier.
Example:
USERID DC C’USER01’ string”user01”
B DC F’100,20’ 2 full words with values 100,200
…. .... …. ….
MONTHS DC CL3’JAN,FEB,MAR’
month contains 3 byte value.
Assembler Training
• Literals
– A convenient means of introducing constants without the
use of ‘dc’ instruction.
– Storage is allowed for literals at the end of a csect(literal
pool).
– Storage allocation can be forced at any point by”LTORG”
assembler instruction.
– Two literals are the same if their specifications are
identical.
– Assembler translates a literal into a base register and a
displacement.
Assembler Training

• Literals(contd..)
Example:
LOAD L 2,=F’4’
MOVE MVC MSG,=C’**ERR**’
Assembler Training
• Assembler Directives
Commonly used directives
CSECT
– Indicates the beginning of a program.
– Smallest portion of the code which can be relocated.
– A program can have more than one CSECT.
– CSECT ‘S can be continued across CSECT ‘S.
– Separate location counter for each CSECT .
– Symbols are not addressable across CSECT ‘S.
Assembler Training
• Assembler Directives(contd.)
Commonly used directives(contd.)
DSECT
– Dummy control sections.
– To describe the structure of a block of memory with out
actually allocating memory.
– Acts as a template.
– No code is generated.
– DC statement is not allowed in a DSECT.
Assembler Training
DSECT(contd.)
Example:
CUSTOMER DSECT
NUMBER DS CL3
LNAME DS CL10
MNAME DS CL10
STREET DS CL5
CITY DS CL5
ZIP DS CL6
Assembler Training
USING
USING < symbol >,Rn.
– Symbol can be any relocatable symbol defined in the
program.
– ‘*’ can be used in the place of the symbol.
– Fields in the DSECT’S can be accessed after establishing
base with this directive.
Assembler Training
USING(contd.)
– Rn, base register to be used by the assembler for resolving the
symbols in the base displacement form.
– The location counter of the symbol is used as the base from
which displacements are calculated.
– Users responsibility to load the base register with base
register.
– BALR instruction can be used to load the base address.
– Range of a base register is 4096 including the base.
– If the code size is more than 4096 bytes,multiple base
registers have to be used.
Assembler Training
USING(contd.)
Example:
BALR R12,0 load the base address
USING *,12 reg 12 is the base register.
USING PROG,10 base for DSECT PROG
Assembler Training
ORG
ORG <expr>
• If expr is specified ,location counter is set with expr
value.
• If expr is not specified ,location counter takes
previous maximum value.
Assembler Training
ORG(contd.)
– Used to redefine the storage.
Example:
BUFFER DS 100F
ORG BUFFER
BUFF1 DS CL80
BUFF2 DS CL80
Assembler Training
DROP
DROP (R0,R1,….,Rn)
Specified registers are dropped as base registers.
END
Signals the end of a control section or program.
EJECT
Force a form feed.
Starts of with a fresh page.
Assembler Training
Data transfer instructions

Assembler Training
Load register
LR R1,R2
– Loads the content of R2 to R1.
– The condition code remains unchanged.
Assembler Training
Load and test register
LTR R1,R2
• Loads the contents of register R2 to R1.
• Condition codes are set depending on the value loaded.
• A register can be checked for zero/non zero value by “ LTR
R1,R1”.
CC INTERPRETATION
00 zero
01 negative
02 positive
03 overflow
Assembler Training
Load complement register
LCTR R1,R2
• Two’s complement R2 is loaded to R1.
• Condition codes are set.
Load negative
LNR R1,R2
• Two’s complement of absolute value of R2 is loaded to R1.
Assembler Training
Load Positive
LPR R1,R2
• Absolute value of R2 is loaded to R1.
Load
L R1,D2(X2,B2)(Rx)
• D2(X2,B2) specifies the address of the second operand .
• The second operand is loaded to the first operand ,specified by
R1.
Assembler Training
Load(contd.)
• Condition code is unchanged.
• Second operand can also be specified as
• S2, a symbol.
• S2(X2),a symbol with index.
• D2,absolute value (maximum value 4095).
• D2(,B2),base displacement form.
• D2(X2),index and displacement.
Assembler Training
Load Halfword
LH R1,D2(X2,B2)
• Sixteen bit quantity specified by the second operand is sign

extended and placed at the first operand location.
Assembler Training
Load Multiple
LM R1,R3,D2(B2) (RX)
• R1 and R3 specifies a range of general registers.
• The set of GPR’s starting with R1 and ending with R3 are
loaded from storage beginning at the location specified by the
second operand.
• The GPR’s are loaded in ascending order.
• Used to restore the environment in subroutine call.
Assembler Training
Load Address
LA R1,D2(X2,B2)(RX)
• The address specified by X2,B2 and d2 is placed in GPR R1.
• In amode 24,bits 0-7 are set to zero.
• In amode 31,bit 0 is zero.
• The condition code is unchanged.
• Used to load a register with an absolute value 0-4095 by
specifying only the displacement.
Assembler Training
Load Address (contd.)
• Used to increment a register by values 1 to 4095 by
specifying the increment value as the displacement and R1&
B2 as same register with X2=0.
Example:
LA 2,25 reg2 <-- 25
LA 3,1(3) reg3 <-- reg3+1..
Assembler Training

Store
ST R1,D2(X2,B2) (Rx)
• The first operand is placed unchanged at the second operand
location.
• The contents of R1 is placed at the second operand location.
• The condition code is unchanged.
Assembler Training

Store Multiple
STM R1,R3,D2(B2) (RX)
• R1 and R3 specifies a range of general registers.
• Registers are considered to be cyclic.
• The set of GPR’s starting with R1 and ending with R3 are loaded
from storage beginning at the location specified by the second
operand.
• The GPR’s are loaded in ascending order.
Example:
STM 14,12,8(13) load register 14,15 & 0-12.
Assembler Training
Arithmetic Instructions
Assembler Training

Add
AR R1,R2 (RR)
A R1,D2(X2,B2) (RX)
• The second operand is added to the first operand and the sum
is placed at the first operand location.
• Condition code is set.
Assembler Training

Add Halfword
AH R1,D2(X2,B2)
• The second operand is added to the first operand and the sum
is placed at the first operand location.
• The second operand is 2 bytes in length and treated as a16-bit
signed binary integer.
• The first operand and the sum are treated as 32-bit signed
binary integer.
Assembler Training

Subtract
SR R1,R2 (RR)
S R1,D2(X2,B2) (RX)
• The second operand is subtracted from the first operand and

the result is placed at the first operand location.
Assembler Training

Subtract Halfword
SH R1,D2(X2,B2)
The second operand is subtracted from the first operand and
result is placed at the first operand location.
• The second operand is 2 bytes in length and treated as a16-bit
signed binary integer.
• The first operand and the sum are treated as 32-bit signed
binary integer.
Assembler Training

Multiply
MR R1,R2 (RR)
M R1,D2(X2,B2) (RX)
The multiplicand and the multiplier are 32-bit signed integer.
• R1 designates the even odd register pair.
• Register R1+1 is multiplied with the second operand and the
product is placed at R1 and R1+1.
• The product is 64 signed binary integer.
• Condition code remains unchanged..
Assembler Training

Multiply Halfword
MH R1,D2(X2,B2)
• The second operand is a 16-bit signed binary integer.

• The first operand is multiplied by the second operand and the
product is placed at the operand location.
• The multiplicand (R1) and the product are 32-bit signed
binary integer.
Assembler Training

Divide
DR R1,R2 (RR)
D R1,D2(X2,B2) (RX)
• R1 designates the even odd register pair.
• The 64 -bit first operand is divided by the 32 bit second
operand (divisor).
• Remainder is placed in general register R1.
• Quotient is is placed in general register R1 +1.
• Fixed point -divide exception is recognized ,if the quotient
exceeds the maximum value.
Assembler Training

Compare
CR R1,R2 (RR)
C R1,D2(X2,B2) (RX)
CH R1, D2(X2,B2) (RX)
• The first operand is compared with the second operand ,and

the result is indicated in the condition code .
• The operands are treated as signed binary integers.
Assembler Training
Branch Instructions
Assembler Training
Branch on condition
BCR M1,R2 (RR)
BC M1,D2(X2,B2) (RX)
The instruction address in the current PSW is replaced by the branch
address if the condition code has one of the values specified by
M1;otherwise,normal instruction sequencing proceeds with the updated
instruction address.
• M1 is a four-bit mask
• Each condition codes correspond to each bit of the mask
• If R2 field is zero,no branch is taken
Assembler Training

Branch on condition
• When all four mask bits are zeros,no branch is taken
• More than one bit in the mask can be selected to enable
branch on any of the condition code setting
Condition Code Mask Position Value

0 8
1 4
2 2
3 1
Assembler Training
Branch on condition(contd.)
Assembler supplied mnemonics are available which can generate the conditional branch instruction with the correct
mask bit values.
• BZ, Branch on zero. Mask bits B’1000’
• BM, Branch on minus. Mask bits B’0100’
• BP, Branch on Plus. Mask bits B’0010’
• BO, Branch on overflow. Mask bits B’0001’
Assembler Training
Branch on condition(contd.)
• BNZ, Branch on not zero. Mask bits B’0111’

• BNM, Branch on not minus. Mask bits B’1011’
• BNP, Branch on not plus. Mask bits B’1101’
• BNO, Branch on not overflow. Mask bits B’1110’
• B,unconditional branch. Mask bits B’1111’
• NOP, No Operation.Mask bits B’0000’
Assembler Training

Branch on Count
BCTR R1,R2 (RR)
BCT R1,D2(X2,B2)(RX)
A one is subtracted from the first operand.When the result
is non-zero branch is taken to the address specified in the
second operand.If zero,normal instruction sequencing
proceeds.
Assembler Training

Branch on Count(contd.)
The first operand and the result are treated as 32-bit binary
integer.
• Overflow is ignored
• When the R2 field is zero no branch is taken
• Can be used to decrement a register by 1
Example
DECRMNT BCTR 2,0 reg2 <---- reg2 - 1
Assembler Training

Branch on Index High
BXH R1,R3,D(B2) (RS)
• R3 register contains the increment value if it is even and
R3+1 register contains the limiting value
• R3 register contents are used for incrementing and as the
limiting value,when it is odd
• The increment value is added to reg R1
• If the sum is greater than the limiting value,branch is taken
Assembler Training

Branch on Index Low or Equal
BXLE R1,R3,D(B2) (RS)
• R3 register contains the increment value if it is even and R3+1
register contains the limiting value
• R3 register contents are used for incrementing and as the
limiting value,when it is odd
• The increment value is added to reg R1
• If the sum is less than or equal to the limiting value,branch is
taken
Assembler Training
Branch and Link
BALR R1,R2 (RR)
BAL R1,D2(X2,B2)(RX)
• Information from current PSW including the updated address is loaded
to reg R1
• R2/D2(X2,B2) specifies the branch address
• If Reg 0 specified for R2,no branch is taken
• If AMODE is 24,the information contains ILC,CC,program-mask bits
0-7 and the address in bits 8-31
Assembler Training
Branch and Link(contd.)
• If AMODE is 31 bit 0 is 1,and rest contains the address
• Used to load the register with the address of next instruction by
specifying R2 as 0
Example
BALR R14,R15 Reg 14<-- next inst. addr. Branch to
R15
BALR R12,0 Reg 12<-- next inst. Addr.
No Branch
Assembler Training
Character Manipulation Instructions

Assembler Training

Insert Character
IC R1,D2(X2,B2) (RX)
The byte at the second-operand location is inserted
into bit positions 24-31 of general register R1.The
remaining bits are unchanged.
Assembler Training
Insert Character under Mask
ICM R1,M3,D2(X2,B2) (RS)
Bytes from contiguous locations beginning at the second-
operand addresses are inserted into reg R1 under control of a mask.
• Mask is 4 bit field.Each bit corresponds to one byte in the register.
• Length of the second-operand in bytes is number of ‘1’s in the
mask
Store Character
STC R1,D2(X2,B2)(RX) Bit 24-31 are stored at the second-
operand location
Assembler Training
Store Character under Mask
STCM R1,M3,D2(X2,B2) (RS)
• Bytes selected from general register R1 under control of a
mask are stored
• Mask is 4 bit field.Each bit corresponds to one byte in the
register
• Length of the second-operand in bytes is number of ‘1’s in
the mask
Assembler Training
Compare Logical Character under Mask
CLM R1,M3,D2(X2,B2) (RS)
• Bytes selected from general register R1 under control of a

mask are compared with bytes from the storage
• Mask is 4 bit field.Each bit corresponds to one byte in the
register
Assembler Training
Compare Logical Character under Mask(contd.)
Example
• Get 1st & 2nd bytes
ICM 2,’1010’,PATRN1
• Get 2nd & 3rd bytes
ICM 3,’0110’,PATRN1
IC 2,PATRN1+3
• Save 1st, 3rd ,4th bytes
STCM 2,’1011’,PATRN2
:
PATRN1 DC CL4’ABCD’
PATRN2 DC CL4
Assembler Training
Move Characters
MVC D1(L,B1),D2(B2)
• L+1 bytes are moved from second operand to first operand
• Each operand is processed left to right
Move Characters Inverse
MVCIN D1(L,B1),D2(B2)
• L+1 bytes are moved from second operand to first operand
• D2(B2) Specifies the address of the rightmost byte
• First operand is processed left to right
• Second operand is processed right to left
Assembler Training
Bit Manipulation Instruction

Assembler Training

Logical AND
NR R1,R2 (RR)
N R1,D2(X2,B2) (RX)
NI D1(B1),I2 (SI)
NC D1(L,B1),D2(B2) (SS)
• The AND of the first operand and second operands is placed
at the first-operand location
• Logical AND is performed bit by bit
• For NC,each operand is processed left to right and L specifies
the number of bytes
Assembler Training
Logical AND
• I2 is one byte immediate value
• Used to turn off the selected bits
Example
NI 2,B’1010000’
Logical OR
OR R1,R2 (RR)
O R1,D2(X2,B2) (RX)
OI D1(B1),I2 (SI)
OC D1(L,B1),D2(B2) (SS)
Assembler Training
Logical OR(contd.)
• The OR of the first operand and second operands is placed at the
first-operand location
• Logical OR is performed bit by bit
• For OC,each operand is processed left to right and L specifies the
number of bytes
• Used to turn off the selected bits
Example
OI 2,B’1010000’
Assembler Training
Exclusive OR (XOR)
XR R1,R2 (RR)
X R1,D2(X2,B2) (RX)
XID1(B1),I2 (SI)
XC D1(L,B1),D2(B2) (SS)
• The XOR of the first operand and second operands is placed at the
first-operand location
• Logical XOR is performed bit by bit
• For XC,each operand is processed left to right and L specifies the
number of bytes
• Can be used to invert the selected bits value
Assembler Training
Compare Logical
CLR R1,R2 (RR)
CL R1,D2(X2,B2) (RX)
CLI D1(B1),I2 (SI)
CLC D1(L1,B1),D2(B2) (SS)
• The first operand is compared with second operand and the
result is indicated in the condition code
• The operands are treated as unsigned binary integers
• I2 is the 8-bit immediate value
Assembler Training
Logical Shift
SLL R1,D2(B2) shift left single logical
SLDL R1,D2(B2) shift left double logical
SRL R1,D2(B2) shift right single logical
SRDL R1,D2(B2) shift right double logical
• Sign bit also participates in the shift operation.
• Vacated bit positions are filled with zero.
• Single shift instruction operates on single register.
• Double shift operation works on register pair.
• Right most 6 bits of D2(B2) indicates the number of bits to be shifted.
• Condition code remain unchanged.
Assembler Training
Arithmetic Shift
SLA R1,D2(B2) shift left single arithmetic
SLDA R1,D2(B2) shift left double arithmetic
SRA R1,D2(B2) shift right single arithmetic
SRDA R1,D2(B2) shift right double arithmetic
• Sign bit does not participate in the shift operation.
• Sign bit is propagated as the fill bit in the right shift operation.
• Single shift instruction operates on single register.
• Double shift instruction operates on register pair.
• Right most 6 bits of D2(B2) indicates the number of bits to be
shifted.
• Condition code setting is like arithmetic instructions.
Assembler Training
Arithmetic Shift (contd.…)
Example : Inverse the bit sequence
LA 1,32(0)Loop count value
L 2,PATRN Get the pattern
LOOP SRDL 2,1(0) Shift bit 31 of R2 to bit 0 of R3
LR 5,3 Get the bit in R5
SLDL 4,1(0) Shift bit 0 of R5 to bit 31 of R4
BCT 1,LOOP Repeat 32 times
ST 4,PATRN
BR 14
PATRN DC F’2435324’
Assembler Training
Logical arithmetic instructions

Assembler Training
The operands are treated as unsigned binary integers.
Add Logical
ALR R1,R2
AL R1,D2(X2,B2)
• The second operand is replaced by the sum of the two operands.
• Condition codes are changed
CC = 00 if sum is zero and no carry
CC = 01 if sum is not zero and no carry
CC = 10 if sum is zero and carry
CC = 11 if sum is not zero and carry
• Used in address arithmetic.
Assembler Training
Subtract Logical
SLR R1,R2
SL R1,D2(X2,B2)
• The second operand is subtracted from the first and the difference
replaces the first operand.
• Condition codes are changed
CC = 00 cannot occur
CC = 01 if difference is not zero and no carry
CC = 10 if difference is zero and carry
CC = 11 if difference is not zero and carry
Assembler Training
Decimal instructions
Assembler Training

Decimal Instructions
• Decimal operands always reside in storage (SS format).
• May be represented in either zoned or packed format.
• Both the formats are of variable length.
• Length of each operand is specified in the instructions.
• Valid digit codes 0 -9.
• Codes A,C (preferred), E,F denotes positive sign.
• Codes B and D (preferred) denotes negative sign.
• Operands should not overlap.
• Operands can have coincident rightmost bytes.
Assembler Training

Decimal Number Formats
Zoned Format
– Rightmost four bits of a byte are numeric bits (N).
– Leftmost four bits are zoned bits.
– Leftmost four bits of the rightmost byte of a decimal number contains the sign.
– Suitable for input/output.
– No decimal-arithmetic instructions operate directly on this format.
Packed Format
– Each byte contains two decimal digits (D).
– Rightmost digit in the rightmost byte contains the sign.
– Maximum length of the operand is 16 bytes (31 digits + 1 sign).
– Decimal-arithmetic instructions always operate on the decimal number in this
format.
Assembler Training

Decimal Arithmetic Instructions
Add Decimal
AP D1(L1,B1),D2(L2,B2)
• Sum of the two operands replaces the first operand.
• All sign and digit codes are checked for validity
Subtract Decimal
SP D1(L1,B1),D2(L2,B2)
• Second operand is subtracted from the first operand and the result
replaces the first operand.
• All sign and digit codes are checked for validity.
Assembler Training

Compare Decimal
CP D1(L1,B1),D2(L2,B2)
• Both the operands are compared and result is indicated in the
condition code.
• All sign and digit codes are checked for validity
Zero and Add Decimal
ZAP D1(L1,B1),D2(L2,B2)
• First operand is initialized with zero.
• The second operand is placed in the first operand location.
• Validity checking is done for the second operand only.
• The two operands may overlap
• Used to move decimal numbers to uninitialized storage locations.
Assembler Training
Multiply Decimal
MP D1(L1,B1),D2(L2,B2)
• First operand is replaced with the product of two operands.
• Multiplier (second operand) length cannot exceed 15 digits and
sign.
Divide Decimal
DP D1(L1,B1),D2(L2,B2)
• First operand is divided by the second operand.
• Divisor (second operand) length cannot exceed 15 digits and sign.
• Divisor length should be less than dividend length.
• Quotient is placed in the leftmost L1-L2 bytes of the first operand.
• Remainder occupies rightmost L2 bytes of the first operand.
Assembler Training

Shift Round Decimal
SRP D1(L1,B1),D2(B2),I3
• Bits 26-31 of D2(B2) is a six-bit signed binary integer, the
magnitude gives the shift value, positive sign for left shift and
negative for right shift.
• I3 is used as a decimal rounding digit.
• Sign digit does not participate in the shifting.
• Vacated digits are filled with zero.
Assembler Training

Decimal Data Transfer Instructions
Move Zones
MVZ D1(L,B1),D2(B2)
• Zone of each byte of operand 2 is moved to the zones of operand 1.
• Operands can overlap
Move Numerics
MVN D1(L,B1),D2(B2)
• Rightmost 4 bits of each byte in the second operand are placed in the
rightmost 4 bits of the corresponding byte of the first operand.
• Operands can overlap.
Assembler Training
Data conversion
Assembler Training
Data Conversion Instructions
Pack
PACK D1(L1,B1),D2(L2,B2)
• Second operand is in zoned decimal format.
• The operand is converted from zoned format to packed format.
Unpack
UNPK D1(L1,B1),D2(L2,B2)
• Second operand is in packed decimal format.
• The operand is converted from packed format to zoned format.
• Digits are not checked for validity.
Assembler Training

Convert to Binary
CVB R1,D2(X2,B2)
• Second operand is in packed decimal format and occupies 8 bytes.
• Data is converted from packed decimal to binary.
• Digits are checked for valid digits and sign.
• If the converted value exceeds 32-bit signed binary integer, a fixed
point divide exception is raised.
• The condition code remains unchanged.
Assembler Training

Convert to Decimal
CVD D1(L1,B1),D2(L2,B2)
• Value in R1 is converted to packed decimal and stored at
D2(X2,B2).
• Second operand occupies 8 bytes of storage.
• The condition code remains unchanged.
Assembler Training
Editing Decimal Data
ED D1(L,B1),D2(X2,B2)
• The source, in the packed format is edited according to the pattern
in the first operand and edited output replace the patterns.
• Features
• Suppression of leading zeroes.
• Insertion of decimal point and commas.
• Inclusion of ‘CR’,’-’ etc.
• conversion of last byte to print as digit.
• Replacing leading zeroes by ‘*’ for check protection.
• Pattern
• Digit selector (X’20’).
• Significance starter (X’21’).
• Fill character (First byte in pattern).
• Insertion symbols (X’6B’ for comma and X’4B’ for decimal point
Assembler Training
Editing Decimal Data(contd.…)
• Leading zeroes are replaced with fill character until a nonzero digit
is encountered, or a significance starter is encountered.
• If significance indicator is on, ‘,’ & ‘.’ are left as it is else replaced
by fill character.
• Positive sign turns off significance.
• Negative sign leaves it as it is.
Edit and Mark
EDMKD1(L,B1),D2(B2)
• All the functions of ED.
• Loads address of first significant byte into register 1.
Assembler Training
Special instructions
Assembler Training
Special Instructions
Translate
TR D1(L,B1),D2(B2)
TR SOURCE(L),TABLE
• Each byte source specifies the table entry which replaces itself in
source.
• Translates the source characters into the values found at the address
offsets in the second operand table one byte at a time.
• The table can have maximum of 256 entries.
• Can be used to translate data from one format to another.
• Can be used to rearrange a record layout.
Assembler Training
Translate and Test
TRT D1(L,B1),D2(B2)
TRT SOURCE(L),TABLE
• Only searches for any specified character(s) in the source.
• Does not change the source.
• Zeroes in the table for no scan.
• Register 1 contains address of the last byte translated.
• Register 2 contains table entry contents (24-31 bits, function byte)
• can be used to find occurrence and position of an invalid character.
• Condition code setting is
• 0 - all function bytes zero
• 1 - non-zero function byte; source not exhausted
• 2 - non-zero function byte; source exhausted
• 3 - ---
Assembler Training
Execute
EX R1,D2(X2,B2)
• Bits 8-15 of the instruction designated by the second-operand
address are ORed with bits 24-31 of R! and the resultant
instruction is executed.
• The ORing does not change either the contents of R1 or the
instruction in storage.
• The target instruction may be 2,4 or 6 bytes in length.
• The execution and exception handling of the target instruction are
exactly as if the target instruction were obtained in normal
operation.
• The instruction address of the current PSW is increased by length
of the EXECUTE instruction.
• The target instruction can not be ‘EXECUTE’ instruction.
• Condition codes are set by the target instruction execution.
Assembler Training
Floating point instruction

Assembler Training
Floating Point Number Representation
• consists of a signed hexadecimal fraction and an unsigned seven-

bit binary integer, called as characteristic.
• Characteristic represents signed exponent in excess-64 notation.
• The range of characteristic is -64 to +64
Assembler Training
Normalization
A normalized floating point number has a non-zero leftmost
hexadecimal fraction digit. If one or more leftmost fraction digits
are zeroes, the number is said to be unnormalized.
Unnormalized numbers are normalized by shifting the fraction left,
one digit at a time, until the leftmost hexadecimal digit is non-zero
and reducing the characteristic by the number of hexadecimal
digits shifted.
Addition and subtraction with extended operands, as well as the
multiply,divide and half operations are performed only with
normalization. Addition and subtraction with short or long
operands may be specified as either normalized or unnormalized.
Assembler Training
Floating Point Data format

Three types of format
• Short floating-point numbers
• Represented by 32 bits
• Bit 0 is sign bit
• Bits 1-7 are characteristic
• Bits 8-31 6-digit fraction
• Can reside in storage or in the floating point registers
Assembler Training
• Assembly Language Basics(contd.)
• Long floating-point number
• Bit 0 is sign bit
• Bits 8-63 14-digit fraction
• Can reside in storage or in the floating point registers
• Extended floating-point numbers
• Bit 0 of higher-order 64 bits is the sign bit
• Bits 1-7 of higher order 64 bits contains the characteristic
• Bits 8-63 of high-order 64 bits and bits 72-127 of low order 64 bits contains
the 28-digit fraction
• Can only reside in floating point registers
Assembler Training

Floating Point Instructions
• Floating-point registers 0,2,4,6 are used in the instructions.
• Only left half of FPR is used if short floating point number is
specified.
• FPR 0&2 , 4&6 can be used to contain extended floating point.
• Instructions are available for data loading, arithmetic and
comparison number.
Assembler Training
NON FLOATING POINT INSTRUCTIONS
L, A, S, M, D, ST, LR, DR, LPR, LNR, LCR, LTR, C, CR.
SHORT FLOATING POINT INSTRUCTIONS

LE, AE, SE, ME, DE, STE, LER, AER, SER, MER, DER, LPER,
LNER, LCER, LTER, CE, CER.
LONG FLOATING POINT INSTRUCTIONS

LD, AD, SD, MD, DD, STD, LDR, ADR, SDR, MDR, DDR,
LPDR, LNDR, LCDR, LTDR, CD, CDR.
END OF ASSEMBLER BASICS
Thank You

Assembler Training (Basics) Part - 1

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Assembler Training (Basics)

• What is ASSEMBLY Language?

• Advantages over high-level language

• Advantages over machine language

IBM -370 /XA BASIC MACHINE

• Program Status Word (PSW)

Assembly Language Basics

– Not Free format

• Assembly Statement Format (contd.)

Assembler supports three types of instructions

Assembly Language Basics(contd.)

5.SI type instruction

Self Defining Terms(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Data transfer instructions

• Sixteen bit quantity specified by the second operand is sign

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

• The second operand is subtracted from the first operand and

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

• The second operand is a 16-bit signed binary integer.

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

• The first operand is compared with the second operand ,and

Assembly Language Basics(contd.)

Condition Code Mask Position Value

• BNZ, Branch on not zero. Mask bits B’0111’

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Character Manipulation Instructions

Assembly Language Basics(contd.)

• Bytes selected from general register R1 under control of a

Bit Manipulation Instruction

Assembly Language Basics(contd.)

Logical arithmetic instructions

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Assembly Language Basics(contd.)

Floating point instruction

Floating Point Number Representation

• consists of a signed hexadecimal fraction and an unsigned seven-

Floating Point Data format

Assembly Language Basics(contd.)

SHORT FLOATING POINT INSTRUCTIONS

LONG FLOATING POINT INSTRUCTIONS

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