Analog and Digital VLSI Design

EEE F313/INSTR F313

Lecture 21: Timing Analysis of sequential Circuits

 Sequential Circuits
Latch

Flip-flop
 D-Latch

CLK

Q
 D-Flip-Flop

CLK

Q
 Synchronous timing Basics
R1 R2
In Combinational
D Q D Q
logic

tclk1 tclk2
clk
tc-q, tsu, tcomb
thold

Under ideal conditions (i.e., when tclk1 = tclk2)

T tc-q + tcomb+ tsu
thold tcomb + tc-q
 Delay Definitions
tpdr: rising propagation delay
From input to rising output crossing VDD/2 (upper
bound)

tpdf: falling propagation delay

From input to falling output crossing VDD/2 (upper
bound)

tpd: average propagation delay

tpd = (tpdr + tpdf)/2
 Delay Definitions
tcdr: rising contamination delay
From input beginning to change to output beginning
to rise (lower bound)

tcdf: falling contamination delay

From input beginning to change to output beginning
to fall (lower bound)

tcd: average contamination delay

tcd = (tcdr + tcdf)/2
 Min-max delays
R1 R2
In Combinational
D Q D Q
logic

tclk1 tclk2
clk
tc-q, tsu, tcomb
thold

R1 R2
In Combinational
D Q D Q
logic

tclk1 tclk2
clk
tc-q, tsu, tplogic, tcdlogic
thold tcdreg
 Synchronous timing Basics
Underreal conditions, the clock signal can
have both spatial (clock skew) and
temporal (clock jitter) variations

Skew is constant from cycle to cycle

Jitter causes T to change on a cycle-by-cycle

basis
 Synchronous timing Basics
Which is more important Set Up Time or Hold Time

T tc-q + tcomb+ tsu

thold tcomb + tc-q
 Positive Clock Skew
R1 R2
Clock and data Combinational
In D Q D Q
flow in the logic
same
tclk1 tclk2
direction clk
delay
T
T+
1 3
>0

2 4

+ thold

T + tc-q + tplogic + tsu so T tc-q + tplogic + tsu -

thold + tcdlogic + tcdreg so thold tcdlogic + tcdreg -
 Negative Clock Skew
Clock and data R1 R2
flow in In D Q
Combinational
D Q
opposite logic
directions tclk1 tclk2
clk
delay
T
T+
1 3

2 4
<0

T + tc-q + tplogic + tsu so T tc-q + tplogic + tsu -

thold + tcdlogic + tcdreg so thold tcdlogic + tcdreg -
 Clock Jitter
Jitter causes T to vary R1
on a cycle-by-cycle Combinational
basis In logic
tclk
clk
T

-tjitter -tjitter

T tc-q + tplogic + tsu + 2tjitter thold tcdlogic + tcdreg 2tjitter

 Combined effect of skew and Jitter
R1 R2
In Combinational
D Q D Q
logic
tclk1 tclk2
T
T+
1
>0

6 12
-tjitter

T tc-q + tplogic + tsu - + 2tjitter thold tcdlogic + tcdreg 2tjitter

 Skew and Jitter
4 power supply
3 interconnect
clock 6 capacitive load
1
generation
7 capacitive
PLL coupling
2 clock drivers

5 temperature

Skew Jitter
manufacturing device clock generation
variations in clock drivers capacitive loading and
interconnect variations coupling
environmental variations environmental variations
(power supply and (power supply and
temperature) temperature)
 Clock Distribution Networks
Clock skew and jitter can ultimately limit the performance of a
digital system, so designing a clock network that minimizes
both is important
In many high-speed processors, a majority of the dynamic power is
dissipated in the clock network.
To reduce dynamic power, the clock network must support clock gating
(shutting down (disabling the clock) units)

Clock distribution techniques

Balanced paths (H-tree network, matched RC trees)
- In the ideal case, can eliminate skew

Clock grids
- Typically used in the final stage of the clock distribution network
 H-Tree

Can insert clock gating at

multiple levels in clock tree
Can shut off entire sub tree
if all gating conditions are
Clock satisfied

Idle
condition
Gated
Clock clock
 Dealing with Jitter and Skews
To minimize skew, balance clock paths using H-tree or matched-tree
clock distribution structures.
If possible, route data and clock in opposite directions; eliminates
races at the cost of performance.
The use of gated clocks to help with dynamic power consumption
make jitter worse.
Shield clock wires (route power lines VDD or GND next to clock
lines) to minimize/eliminate coupling with neighboring signal nets.
Use dummy fills to reduce skew by reducing variations in
interconnect capacitances due to interlayer dielectric thickness
variations.
Beware of temperature and supply rail variations and their effects
on skew and jitter. Power supply noise fundamentally limits the
performance of clock networks.
Thank You