Infineon M167 16-bit Microcontroller

One of a family of microcontrollers (M16x)

Derived from M166
Same 16-bit CPU core in all family members
Provides software compatability e.g. The Keil C166 C
compiler can be used for all devices in the family.
Allows migration of software
The 167CS is a quite advanced microcontroller
with many peripherals and functions.
Most microcontrollers only have some of the
features of the 167CS, a few could have more.

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M167CS Functional Block Diagram

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M167CS CPU Block Diagram

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Infineon M167 Basic Features
High Performance 16-bit CPU with Four-Stage
Pipeline
Control Oriented Instruction Set with High
Efficiency
Integrated On-Chip Memory
External Bus Interface
16-Priority-Level Interrupt System
8-Channel Peripheral Event Controller (PEC)
Intelligent On-Chip Peripheral Subsystems

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Infineon M167 Basic Features contd.
111 I/O lines, bit addressable, organised :-
one 16-bit I/O port (Port 2)
eight 8-bit I/O ports : P0H and P0L making 16-bit Port
0, P1H and P1L making 16-bit Port1, Port 4, Port 6,
Port 7and Port 8
one 15-bit I/O port (Port 3)
one 16-bit input only port (Port 5)
Most port lines have alternate functions
Tri-stated in input mode
Selectable input thresholds (not on all pins)
Push/pull or open drain output mode

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Basic Features contd.
High Performance 16-bit CPU with Four-Stage Pipeline
80/60 ns minimum instruction cycle time, with most
instructions executed in 1 cycle
400/300 ns multiplication (16-bit * 16-bit), 800/600 ns
division (32-bit/16-bit)
Multiple high bandwidth internal data buses
Register based design with multiple variable register banks
Single cycle context switching support
16 MBytes linear address space for code and data (Von
Neumann architecture)
System stack cache support with automatic stack
overflow/underflow detection
[the indicated timings refer to a CPU clock of 25/33 MHz]

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Basic Features contd.
Control Oriented Instruction Set with High
Efficiency
Bit, byte, and word data types
Flexible and efficient addressing modes for high code
density
Enhanced boolean bit manipulation with direct
addressability of 6 Kbits for peripheral control and
user defined flags
Hardware traps to identify exception conditions during
runtime
HLL support for semaphore operations and efficient
data access

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Integrated On-Chip Memory
3 KByte internal RAM for variables, register
banks, system stack and code.
8 KByte on-chip high-speed XRAM for variables,
user stack and code.
32 KByte on-chip ROM (not for ROMless
versions) for code and fixed data.

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3 KByte on-chip Internal RAM (IRAM)
Has multiple uses :-
user defined variables
the system stack
general purpose register banks
A register bank can consist of up to 16 word-wide (R0 to
R15) and/or byte-wide (RL0, RH0,, RL7, RH7) so-called
General Purpose Registers (GPRs).
and can even be used for program code.
Special Function Registers (SFRs)
1024 bytes (2 * 512 bytes) of the address space are reserved for
SFRs. SFRs are word-wide registers which are used for
controlling and monitoring functions of the different on-chip units.
Unused SFR addresses are reserved for future members of the
C166/167 Family.

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8 KBytes of on-chip Extension RAM (XRAM)
Organized as two blocks of 2 KByte and 6 KByte.
XRAM provides storage for user data, user stacks, or
code.
XRAM is accessed like external memory and therefore
cannot be used for the system stack or for register banks
and is not bit addressable.
The XRAM permits 16-bit accesses with maximum
speed.
In order to meet the needs of designs where more
memory is required than is provided on chip, up to 16
MBytes of external RAM and/or ROM can be connected
to the microcontroller.

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External Bus Interface
Multiplexed or demultiplexed bus configurations
Segmentation capability and chip select signal
generation
8-bit or 16-bit data bus
Bus cycle characteristics selectable for five
programmable address areas
Single Chip Mode when no external memory is required,
16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

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16-Priority-Level Interrupt System
56 interrupt nodes each with separate interrupt
vectors
240/180 ns typical interrupt latency (400/300 ns
maximum) in case of internal program execution
Fast external interrupts

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8-Channel Peripheral Event Controller(PEC)

The PEC provides a sort of DMA capability

Interrupt driven single cycle data transfer
Transfer count option (std. CPU interrupt after
programmable number of PEC transfers)
Eliminates overhead of saving and restoring
system state for interrupt requests

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Intelligent On-Chip Peripheral Subsystems
24-channel 10-bit A/D Converter with
programmable conversion time (7.76 us min.)
Two 16-channel Capture/Compare Units with 2
independent time bases. Useful for pulse and
waveform generation e.g. Ingition firing
sequence for a car engine.
4-channel Pulse width Modulation(PWM) unit
Two General Purpose Timer Units
GPT1: Consisting of three 16-bit timers/counters,
maximum resolution fCPU/8
GPT2: Consisting of two 16-bit timers/counters,
maximum resolution fCPU/4

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Intelligent On-Chip Peripheral Subsystems

Asynchronous/Synchronous Serial Channels

(USART) with baud rate generator, parity,
framing, and overrun error detection
High Speed Synchronous Serial Channel
programmable data length and shift direction
Two on-chip CAN Bus Modules(V 2.0B) active
Real Time Clock
Watchdog Timer with programmable
time intervals
Bootstrap Loader for flexible system initialization

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Other features
Different Temperature Range Devices
0 to + 70 C, 40 to + 85 C, 40 to + 125 C
Infineon CMOS Process
Low power CMOS technology including power
saving Idle and Power Down modes
144-pin Plastic Metric Quad Flat Pack (MQFP)
Package
P-MQFP, 28 28 mm body, 0.65 mm (25.6 mil) lead
spacing,surface mount technology.

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Acronyms
ADC Analogue to Digital Converter
ALE Address Latch Enable
ALU Arithmetic and Logic Unit
ASC Asynchronous/synchronous
Serial Controller
CAN Controller Area Network
(License Bosch)
CAPCOM CAPture and COMpare unit
CISC Complex Instruction Set
Computing
CMOS Complementary Metal Oxide
Silicon
CPU Central Processing Unit
EBC External Bus Controller
ESFR Extended Special Function
Register
Flash Non-volatile memory that may
be electrically erased
GPR General Purpose Register
GPT General Purpose Timer unit
HLL High Level Language
IO Input/Output
OTP One Time Programmable
memory
PEC Peripheral Event Controller
PLA Programmable Logic Array
PLL Phase Locked Loop
PWM Pulse Width Modulation
RAM Random Access Memory
RISC Reduced Instruction Set
Computing
ROM Read Only Memory
RTC Real Time Clock
SDD Slow Down Divider
SFR Special Function Register
SSC Synchronous Serial Controller
WDT Watch Dog Timer
XBUS Internal representation of the
External Bus
XRAM On-chip extension RAM
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