Fundamental Concepts

Processor fetches one instruction at a time and

perform the operation specified.
Instructions are fetched from successive
memory locations until a branch or a jump
instruction is encountered.
Processor keeps track of the address of the
memory location containing the next
instruction to be fetched using Program
Counter (PC).
Instruction Register (IR)
 Micro Operations for Fetch Cycle
Occurs at the beginning of each instruction cycle.
Causes an instruction to be fetched.
Registers involved AR, PC, DR and IR.
S.No Micro-operation Description

1 AR PC Add of the next ins. to be fetched. Load this in AR

2 DR Mem Address is available on the add bus, read command

from ctrl unit copies the contents from that loc into DR
3 PC PC+1 Increment PC, to point to the next ins.

4 IR DR DR contents copied to IR (Decoding)

 At beginning PC : 0000 0000 0110 0100

MAR 0000 0000 0110 0100 MAR 0000 0000 0110 0100
MDR MDR 0001 0000 0010 0000
PC 0000 0000 0110 0100 PC 0000 0000 0110 0100
IR IR
ACC ACC

First Step Second Step

Continued.

MAR 0000 0000 0110 0100 MAR 0000 0000 0110 0100
MDR 0001 0000 0010 0000 MDR 0001 0000 0010 0000
PC 0000 0000 0110 0101 PC 0000 0000 0110 0101
IR IR 0001 0000 0010 0000
ACC ACC

Third Step Fourth Step

Register Transfers
Internal processor
Bus
R i in

R i

R i out

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out
 Fetching a Word from Memory
Address into MAR; issue Read operation; data into MDR.
Memory-bus Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Connection and control signals for register MDR.

 Performing an Arithmetic or Logic Operation
The ALU is a combinational circuit that has no
internal storage.
ALU gets the two operands from MUX and
bus. The result is temporarily stored in
register Z.
What is the sequence of operations to add
the contents of register R1 to those of R2 and
store the result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
 Execution of a Complete Instruction
Add (R3), R1
Fetch the instruction
Fetch the first operand (the contents
of the memory location pointed by
R3)
Fetch the second operand, R1
Perform the addition
Load the result into R1
 Execution of a Complete Instruction Control Signals

4200 : Add (R3), R1 PC

. ......

Step Action Instruction

MAR Decoder &
1 PCout MARin Read Select 4 Add Zin Mem Bus Control Logic

MDR
2 Zout PCin Yin WMFC

Y IR
3 MDRout IRin Constant 4

4 R3out MARin Read

Select R0
MUX
5 R1out Yin WMFC
R1
ALU Add
6 MDRout Select Y Add Zin Ctrl Sub A B
R3

. . ..
Signals
ALU

. . ..
7 Zout R1in XOR

Rn-1
Z
Temp

Single bus organization of the datapath inside the processor

 Execution of Branch Instructions
A branch instruction replaces the contents of
PC with the branch target address, which is
usually obtained by adding an offset X given
in the branch instruction.
The offset X is usually the difference
between the branch target address and the
address immediately following the branch
instruction.
Conditional branch
 Bus A Bus B Bus C
Incrementer

PC

Register File

Mux
Constant

ALU
Multiple
-Bus
Organization IR

Instruction
Decoder

MDR

MAR

Memory Data
Memory Address
Lines
Lines
 Internal processor
bus
Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Question
Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1
control ALU
lines
Carry -in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

What is the control

sequence for
execution of the
instruction
Add R1, R2
including the
instruction fetch
phase? (Assume
single bus
architecture)
 CONTROL UNIT DESIGN

Hardwired Control

Micro programmed Control

HARDWIRED CONTROL UNIT
Control Unit Organization
CLK Control Step
Counter

.
.
.
. External
. Inputs
. Decoder/
IR . Encoder
. Condition
.
.
. Codes
.
.

Control Signals
 Clock Control Step
Counter
....

Step Decoder

T1 T2 Tn
...
Ins1
External Inputs

...
Ins2
Instruction
...

IR Encoder
...

Decoder
Insm Condition

...
Codes
...

Run (Begin) End (Reset)

Control Signals
 Design Techniques
State Table Method : standard algorithmic
approach.
Delay Element Method : heuristic method
based on the use of clocked delay elements
for control signal timing.
Sequence Counter Method : uses counters
for timing purposes.
PLA Method : uses Programmable Logic
Arrays.
Multiplier Control Unit External Control Signals

Clock Begin End

Multiplicand
C2

Mn-1 .......... M1 M0 C0
Count C
C1
o
C2
Comparator n
0
t
.
. r
C6 C7
. Counter o
.
Cin . l
.
C5
. U
C0 C1
n-bit Adder C9
n
i
C10
C4 t

C8
Multiplier

An-1 .......... A1 A0 Qn-1 .......... Q1 Q0 Q-1

C9
C3
C10 C0

IN BUS

OUT BUS
Control Signals for the 2complement multiplier
Control Signal Operation controlled
C0 Clear A, Q-1 and Count (n)
C1 Decrement count
C2 Transfer word on INBUS to M
C3 Transfer word on INBUS to Q
C4 Shift right A, Q & Q-1
C5 2s complement multiplicand
C6 Transfer A to left input of adder
C7 Transfer M to right input of adder
C8 Transfer adder output to A
C9 Transfer A to OUTBUS
C10 Transfer Q to OUTBUS
Accumulator based CPU with Control Points
Sequential Circuit

AR PC C2
IR
C0
C4 C5 C3

C1
Program Control Unit (PCU)
C8

System Bus

DR AC

C6
C7
C9
C10 Arithmetic & Logic Unit (ALU)
C11
C12

Data Processing Unit (DPU)

Control Signals for accumulator-based CPU
Control Signal Operation controlled
C0 AR<-PC
C1 DR<-(M)AR
C2 PC<-PC+1
C3 PC<-DR (Add)
C4 IR<-DR (Opcode)
C5 AR<-DR (Add)
C6 DR<-AC
C7 AC<-DR
C8 (M)AR<-DR
C9 AC<-AC+DR
C10 AC<-AC-DR
C11 AC<-AC (and) DR
C12 AC<-(not) AC