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Register & Shift Register

Register:
A set of n flip-flops
 Each flip-flop stores one bit
Two basic functions:
Data storage and Data movement

Shift Register:
 A register that allows each of the flip-flops to pass the stored
information to its adjacent neighbour

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SHIFT REGISTERS
Shift registers are a type of sequential logic circuit,
mainly for storage of digital data.
A group of flip-flops connected in a chain so that the
output from one flip-flop becomes the input of the
next flip-flop.
Most of the registers possess no characteristic
internal sequence of states.
All flip-flop is driven by a common clock, and all
are set or reset simultaneously.
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Characteristics of Shift Registers
• Number of bits (4-bit, 8-bit, etc.)
• Loading
– Serial
– Parallel (asynchronous or synchronous)
• Common modes of operation.
– Parallel load
– Shift right-serial load
– Shift left-serial load
– Hold
– Clear

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Basic data movement in shift registers

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Basic data movement in shift registers

1 1 1 0
1 0 1 0 1 1 1 0
1 0 1 0

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SERIAL VS PARALLEL

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Storage Capacity

The storage capacity of a register is the total number of bits (1 or 0) of


digital data it can retain. Each stage (flip flop) in a shift register
represents one bit of storage capacity. Therefore the number of stages in
a register determines its storage capacity

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Serial In - Serial Out Shift Registers

 The register is first cleared, forcing all four outputs to zero.


 The input data is then applied sequentially to the D input of the first flip-flop
on the left (FF0).
 During each clock pulse, one bit is transmitted from left to right.
 Assume a data word to be 1001.
 The least significant bit of the data has to be shifted through the register from
FF0 to FF3.
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Four bits (1010) being entered serially into the register

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Four bits (1010) being serially shifted out of the register and replaced
by all zeros

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Parallel in/serial out( parallel out) shift registers

Parallel out
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Applications
 To produce time delay
The serial in -serial out shift register can be used as a time delay
device.
The amount of delay can be controlled by:
1. the number of stages in the register
2. the clock frequency

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To simplify combinational logic
To convert serial data to parallel data

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UNIVERSAL SHIFT REGISTER(IC74194)

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FUNCTIONAL DIAGRAM

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FUNCTIONAL TABLE

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UNIVERSAL SHIFT REGISTER(IC74194)

RIGHT
SELECTION INPUTS LEFT
INPUT INPUT

L H L H L H L H
R O L O R O L O R O L O R O L O
A L A L A L A L
D D D D D D D D

4*1 MUX OUTPUTS


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IC74194-LOGIC DIAGRAM

L H L H L H L H
RO L O R O L O R O L O R O L O
A L A L A L A L
D D D D D D D D
4*1 MUX

DFF
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