Académique Documents
Professionnel Documents
Culture Documents
Digital IC Technologies
Pseudo-NMOS Inverter
• Advantage over CMOS: One MOS transistor per input
• If there are more than one input for the inverter:
• Less area occupied on the chip
• Time-delay associated with numerous inputs is less
ACTIVE LOAD
Figure 15.10 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load (or saturated-load) NMOS inverter. (c) The
depletion-load NMOS inverter.
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
Question: Knowing typically 4<r<10, how do tPLH and tPHL compare? Is the operation
symmetric? Suggest a suitable application for the ratioed inverter.
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15
1. Select r: typically between 4 and 10. Compromise between: Speed, NM, Silicon area
2. Select W/L: Compromise between speed and Power (Istat)
• Typically select: 50mA<Istat<100mA
Viable cases for pseudo-NMOS: When output is mostly high Low static power
ECE-E434
Digital Electronics
Advanced Topics in Digital IC Design – Ch. 15