AAG: An Automatic Assertion Generation

Framework for RTL Design

Shahid Ali Murtza , Osman Hasan, Kashif Saghar

Conference Paper Presentation

iCoMET
IBA Sukkur, Pakistan
March 3, 2018
Outline

 Introduction

 Problem Statement

 Proposed Methodology

 Demo

 Conclusion

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Introduction

 Functional Verification is a necessary for safety critical

projects.

 The verification process can take

upto 60% to 70% of the overall

design effort.

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Introduction

 For Verilog based designs, simulation continues to be the

most commonly used testing technique.

 Traditional Simulation
 Manual testbenches take a lot of time.
 Manual selection of test vectors results in biased testing
 Manual testing can end up erroneous testing setups

Biased Testing, Time Consuming, Human Errors, Costly

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More problems with traditional simulation

 Verification hotspots in complex designs

 Hard-to-verify structures
 Source of error

 Critical Coverage Points

 False sense of security
 Global coverage is not possible

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Solution to Biased Testing Problem

 Random Pattern Generation for Inputs Vectors

 Testbench utilizes directed random testing
 Randomized Testing(RT)
 Automation
 Time saving
 Unbiased testing
 Cost effective

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Solution to other problems

 Assertions specify the conditions about the

intended/prohibited design behavior
 Assertions are put into Verilog RTL design
 Assertions
 Property specification

Randomized Testbench

Assertion Verification Report

 Observability
 Controllability

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Contribution of the Paper

 Automatic Assertion based Verification Framework

for RTL Designs
 Automatic testbench generation
 Automatic assertions generation
 Randomized Testing + Assertions

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Methodology

.v

Automatic

Flow of Assertion Based Verification

RTL Testbench
Verilog Design
Generator
.v

Verilog Randomized Testbench

HDL Simulator .vcd

Simulation Output Data

Automatic
Assertion
Generator .gmvh

SystemVerilog Assertions

SVA Simulator/FV
Report
Assertion Failure Report

Report

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Testbench Generation

Randomized Test bench

.v Testbench .v for input
Generator Verilog file

 Tools for testbench generation

 Commercial Tools
 Open Source
 VerTGen

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Automatic Testbench Generator: VerTGen

 User friendly GUI  Random Test Patterns

 VerTGen  Freeware  Supports both 2000 & 1995 Verilog

 Time saving  Combinational & Sequential Circuits

 Automatic  Generated Testbench Compatible for VCD File

.v
Input Verilog Generation
file

Input/Output User Provided

Port Extraction Parameters

Random Test Initial Seed

Vector Distribution
Generator Range

Clock Period
Clock/
# of Vectors
Reset/Enable
Clock Hold
Event Generator
Value

Testbench
for input Verilog file
.v

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Simulation Data Generation

ModelSim
. v VerTGen Student .vcd
Version

VCD file generation compatible for next module

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Assertion Generation Engine

 Automatic Assertion Generation

 GoldMine (System Verilog Assertions)

 An automatic assertion generation tool by University of

Illinois

. v
GoldMine .gmv

.vcd

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Assertion Testing

 SVA Simulator

 IFV

. v
Verifier .report

.gmv

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DEMO

DEMO

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Demo Example
Two blocks A,B exchange data via a common bus :

 A Grant never occurs without a Request.

Assert never GntA && !ReqA
 If A (B) receives a Grant, then B (A) does not.
Assert always GntA -> !GntB
 A (B) never receives a Grant in two successive cycles.
Assert never GntA && nextGntA
 A Request is eventually followed by a Grant
Assert always ReqA -> eventually GntA
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Step 1: Testbench Generation

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 Input Verilog file  Testbench file
`timescale 1ns/1ps
module arb2(clk, rst, req1, req2, gnt1,
gnt2); module arb2_bench;

reg req2;
input clk, rst; reg req1;
input req1, req2; reg rst;
output gnt1, gnt2; reg clk;

wire gnt2;
reg state; wire gnt1;
reg gnt1, gnt2;
arb2 arb2_ ( .req2(req2),
.req1(req1),
always @ (posedge clk, posedge rst) .rst(rst),
if (rst) .clk(clk),
.gnt2(gnt2),
state <= 0; .gnt1(gnt1));
else initial begin
state <= gnt1; VerTGen $dumpfile("arb2.vcd
$dumpvars(0, arb2_bench.arb2_);
clk = 0;
always @ (*) rst = 1;
if (state) #26 rst = 0;
#500000 $finish;
begin end
gnt1 = req1 & ~req2;
gnt2 = req2; always begin
#25 clk = ~clk;
end end
else
begin always begin
#24;
gnt1 = req1; req2 = $random;
gnt2 = req2 & ~req1; req1 = $random;
end #26;
end
endmodule
endmodule
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Step 2: Initial Simulation (*.VCD FILE)

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Step 3: ASSERTION GENERATION

To run the goldmine in this setup, we need the following two files:
1. Verilog module file
--->keep in the /<GoldMine Directory>/Verilog/<Module Name>/<Module Name>.v
2. Verilog module's Simulation Data (in <Module Name>.vcd format)
---> keep in the /<GoldMine Directory>/goldmine.out/<Module Name>/<Module Name>.vcd
Now, run following command in the terminal in goldmine directory:

xyz@abc$./goldmine verilog/<Module Name>/<Module Name>.v

On successful execution, output files can be found

in goldmine.out/<Module Name>/ folder

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Output file: Assertions

always @ (posedge clk)

begin
no_rst: assume property ( rst == 0 );
gm0 : assert property ( ( req1 == 0 ) |-> ( gnt1 == 0 ) );
gm1 : assert property ( ( req1 == 1 && req2 == 0 ) |-> ( gnt1 == 1 ) );
gm2 : assert property ( ( req1 == 0 ) ##1 ( req1 == 1 ) ##1 ( req2 == 1 ) |-> ( gnt1 == 0 ) );
gm3 : assert property ( ( req1 == 0 ) ##1 ( req1 == 1 ) |-> ( gnt1 == 1 ) );
gm4 : assert property ( ( req1 == 1 && req2 == 0 ) ##1 ( req2 == 1 ) |-> ( gnt1 == 0 ) );
gm5 : assert property ( ( req1 == 1 && state == 0 ) ##1 ( req2 == 1 ) ##1 ( req1 == 1 ) |-> ( gnt1 == 1 ) );
gm6 : assert property ( ( req2 == 1 && state == 1 ) ##1 ( req1 == 1 ) ##1 ( req2 == 1 ) |-> ( gnt1 == 0 ) );
gm7 : assert property ( ( req1 == 1 && req2 == 0 ) ##1 ( req2 == 1 ) ##1 ( req1 == 1 ) |-> ( gnt1 == 1 ) );
gm8 : assert property ( ( req2 == 0 ) |-> ( gnt2 == 0 ) );
gm9 : assert property ( ( req1 == 0 && req2 == 1 ) |-> ( gnt2 == 1 ) );
gm10 : assert property ( ( req1 == 0 ) ##1 ( req1 == 1 ) |-> ( gnt2 == 0 ) );
gm11 : assert property ( ( req1 == 0 ) ##1 ( req1 == 1 ) ##1 ( req2 == 1 ) |-> ( gnt2 == 1 ) );
gm12 : assert property ( ( req1 == 1 && state == 0 ) ##1 ( req2 == 1 ) ##1 ( req1 == 1 ) |-> ( gnt2 == 0 ) );
gm13 : assert property ( ( req1 == 1 && req2 == 0 ) ##1 ( req2 == 1 ) |-> ( gnt2 == 1 ) );
gm14 : assert property ( ( req1 == 1 && req2 == 0 ) ##1 ( req2 == 1 ) ##1 ( req1 == 1 ) |-> ( gnt2 == 0 ) );
gm15 : assert property ( ( req2 == 1 && state == 1 ) ##1 ( req1 == 1 ) ##1 ( req2 == 1 ) |-> ( gnt2 == 1 ) );
end

Generated assertions are in SystemVerilog syntax

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Conclusion

 Faster than the regular simulation

 Increased robustness in testing

 Improved verification efficiency

 Automation in assertion generation

 Cost effective verification solution

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Slide 1

Thanks!

http://save.seecs.nust.edu.pk/projects/VerTGen/