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Course Outcomes:
On completion of the course, student will be able to
● Describe the ARM microprocessor architectures and its feature.
● Interface the advanced peripherals to ARM based microcontroller.
Outline:
1. Interrupt structure of LPC2148
2. Interfacing with LED, LCD
3. Interfacing with KEYPAD, GLCD
4. Simple LPC2148 GPIO Programming examples Using timers of
LPC2148 to generate delay
5. Serial communication programming for transmission and reception
from computer
6. Programming for UART
Outline:
1. Interrupt structure of LPC2148
2. Interfacing with LED, LCD
3. Interfacing with KEYPAD, GLCD
4. Simple LPC2148 GPIO Programming examples Using timers of
LPC2148 to generate delay
5. Serial communication programming for transmission and reception
from computer
6. Programming for UART
Interrupt : “An interrupt is a signal sent to the CPU which
indicates that a system event has a occurred which needs
immediate attention”.
Interrupt ReQuest (IRQ) can be thought of as a special
request to the CPU to execute a function(small piece of code)
when an interrupt occurs.
ISR : This function or ‘small piece of code’ is technically
called an ‘Interrupt Service Routine‘ or ‘ISR’.
So when an IRQ arrives to the CPU, it stops executing the
current code and start executing the ISR. After the ISR
execution has finished the CPU gets back to where it had
stopped.
Interrupts are handled by Vectored Interrupt Controller(VIC)
LPC214x VIC
Features
● ARM PrimeCell Vectored Interrupt Controller
● 32 interrupt request inputs
● 16 vectored IRQ interrupts
● 16 priority levels dynamically assigned to interrupt requests
● Software interrupt generation
Interrupt structure of LPC2148
The VIC is a component from the ARM prime cell.
VIC module is a highly optimised interrupt controller.
The VIC is used to handle all the on-chip interrupt sources from
peripherals.
Each of the on-chip interrupt sources is connected to the VIC on a fixed
channel: your application software can connect each of these channels to
the CPU interrupt lines (FIQ, IRQ) in one of three ways.
Interrupt structure of LPC2148
The VIC allows each interrupt to be handled as an FIQ interrupt, a
vectored IRQ interrupt, or a non vectored IRQ interrupt.
FIQ is the fastest followed by vectored IRQ with non-vectored IRQ
being the slowest.
❖ LPC2148 external interrupt inputs: 4
❖ Processor and on-chip user peripherals generate interrupts
❖ LPC2148 uses ARM PrimeCell (PL190) Vectored Interrupt
Controller for managing interrupts.
❖ When interrupt occurs,
➔ VIC identifies the source of interrupts
➔ Passes requests on interrupt request pins as per the configuration
➔ If more than one interrupt occurs at a time, VIC resolves priority
❖ 32 interrupt request inputs, LPC2148 uses 22 of 32 interrupts
Block diagram of the Vectored Interrupt Controller (VIC)
ARM PrimeCell Vectored Interrupt Controller (PL190)
SFRs
• VICIntSelect (R/W) 0 = IRQ, 1 = FIQ
• VICIntEnable (R/W) Enable Selective Interrupt Source
• VICIntEnClr (R/W) Disable Selective Interrupt Source
• VICIRQStatus (R)to know the status of enabled interrupt
• VICFIQStatus (R)to know the status of enabled FIQ
• VICSoftInt to trigger a software interrupt
• VICSoftIntClear to clear software interrupt
• VICVectCntl0 to VICVectCntl15 Assign interrupt source
• VICVectAddr0 to VICVectAddr15 Assign interrupt address
• VICVectAddr Holds the address of currently active interrupt
• VICDefVectAddr Holds the address of Non-Vectored ISR
Fast Interrupt reQuest (FIQ)
❖ FIQ requests have the highest priority.
❖ Any interrupt source may be assigned as the FIQ interrupt.
❖ The VIC interrupt select register has a unique bit for each
interrupt.
❖ However setting multiple bits in the Interrupt Select Register will
enable multiple FIQ interrupt sources.
❖ On entry the interrupt source can be determined by examining the
VIC FIQ Status register and the appropriate code executed.
❖ Once you have selected an FIQ source the interrupt can be
enabled in the VIC interrupt enable register.
❖ Once an FIQ interrupt is generated, the processor will change to
FIQ mode and vector to 0x0000001C, the FIQ vector.
Leaving An FIQ Interrupt
❖ Before you exit the ISR code you must make sure that any
interrupt status flags in the peripheral have been cleared.
❖ If this is not done you will get continuous interrupts until the flag
is cleared.
Vectored IRQ
❖ Vectored IRQs have the middle priority, but only 16 of the 32
requests can be assigned to this category.
❖ The VIC provides a programmable hardware lookup table which
delivers the address of the C function to run for a given interrupt
source.
❖ Any of the 32 requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15
has the lowest.
❖ Each slot contains a vector address register and a vector control
register.
❖ For a Vectored IRQ the VIC provides a hardware lookup table for
the address of each ISR. The interrupt priority of each peripheral
may also be controlled.
❖ The Vector Control Register contains two fields: a channel field
and an enable bit.
❖ The other register in the VIC slot is the Vector Address Register.
❖ As its name suggests, this register must be initialised with the
address of the appropriate C function to run when the interrupt
associated with the slot occurs.
Leaving An IRQ Interrupt
❖ The interrupt status flags are cleared in the peripheral which
generated the request.
❖ At the end of the interrupt you must do a dummy write to the
Vector Address Register.
❖ This signals the end of the interrupt to the VIC and any pending
IRQ interrupt will be asserted.
Non-Vectored Interrupts
❖ The VIC is capable of handling 16 peripherals as vectored
interrupts and at least one as an FIQ interrupt.
❖ If there are more than 17 interrupt sources on the chip, any extra
interrupts can be serviced as non-vectored interrupts.
❖ The non-vectored interrupt sources are served by a single ISR.
❖ The address of this ISR is stored in an additional vector address
register called the default vector address register.
Leaving A Non-Vectored IRQ Interrupt
❖ As with the vectored IRQ interrupt, you must clear the peripheral
flag and write to the vector address register.
Important Note
Each Peripheral in lpc2148 has only 1 IRQ associated with it.
But inside each device there may be different sources which can raise an
interrupt.
Like the TIMER0 peripheral has 4 match + 4 capture registers and any one
or more of them can be configured to trigger an interrupt.
Hence such devices have a dedicated interrupt register which contains a
flag bit for each of these source(For Timer block its ‘T0IR’).
So , when the ISR is called first we need to identify the actual source of the
interrupt using the Interrupt Register and then proceed accordingly.
Also just before , when the main ISR code is finished we also need to
acknowledge or signal that the ISR has finished executing for the current
IRQ which triggered it.
This is done by clearing the flag(i.e the particular bit) in the device’s
interrupt register and then by writing a zero to VICVectAddr register
which signifies that interrupt has ISR has finished execution successfully.
Outline:
1. Interrupt structure of LPC2148
2. Interfacing with LED, LCD
3. Interfacing with KEYPAD, GLCD
4. Simple LPC2148 GPIO Programming examples Using timers of
LPC2148 to generate delay
5. Serial communication programming for transmission and
reception from computer
6. Programming for UART
LPC214x GPIO
LPC214x Pin connect block
● The purpose of the Pin connect block is to configure the
microcontroller pins to the desired functions.
● The pin connect block allows selected pins of the
microcontroller to have more than one function.
● Configuration registers control the multiplexers to allow
connection between the pin and the on chip peripherals.
● Peripherals should be connected to the appropriate pins prior to
being activated, and prior to any related interrupt(s) being
enabled.
● Selection of a single function on a port pin completely excludes
all other functions otherwise available on the same pin.
● The only partial exception from the above rule of exclusion is the
case of inputs to the A/D converter.
● The Pin Control Module contains registers as shown in Table
below.
Pin function Select register 0 (PINSEL0 - 0xE002 C000)
● The PINSEL0 register controls the functions of the pins as per
the settings listed in Table 40.
● The direction control bit in the IO0DIR register is effective only
when the GPIO function is selected for a pin.
● For other functions, direction is controlled automatically.
● PINSEL0 : PINSEL0 is used to configure PORT0 pins P0.0 to
P0.15.
Pin function Select register 1 (PINSEL1 - 0xE002 C004)
● The PINSEL1 register controls the functions of the pins as per the
settings listed in table.
● The direction control bit in the IO0DIR register is effective only
when the GPIO function is selected for a pin.
● For other functions direction is controlled automatically.
● PINSEL1 : PINSEL1 is used to configure PORT0 pins P0.16 to
P0.31.
Pin function Select register 2 (PINSEL2 - 0xE002 C014)
● The PINSEL2 register controls the functions of the pins as per the
settings listed in Table.
● The direction control bit in the IO1DIR register is effective only
when the GPIO function is selected for a pin.
● For other functions direction is controlled automatically.
● PINSEL2 : PINSEL2 is used to configure PORT1 pins P1.16 to
P1.31.
Pin function select register values
● The PINSEL registers control the functions of device pins as
shown below.
● Pairs of bits in these registers correspond to specific device pins.
LPC214x GPIO
Features
● Every physical GPIO port is accessible via either the group of
registers providing an enhanced features and accelerated port
access or the legacy group of registers
● Accelerated GPIO functions:
➔ GPIO registers are relocated to the ARM local bus so that the
fastest possible I/O timing can be achieved
➔ Mask registers allow treating sets of port bits as a group, leaving
other bits unchanged
➔ All registers are byte and half-word addressable
➔ Entire port value can be written in one instruction
● Bit-level set and clear registers allow a single instruction set or
clear of any number of bits in one port
● Direction control of individual bits
● All I/O default to inputs after reset
● Backward compatibility with other earlier devices is maintained
with legacy registers appearing at the original addresses on the
APB bus
Applications
● General purpose I/O
● Driving LEDs, or other indicators
● Controlling off-chip devices
● Sensing digital inputs
Pin description
PORT0 is a 32-bit port
● Out of these 32 pins, 28 pins can be configured as either general
purpose input or output.
● 1 of these 32 pins (P0.31) can be configured as general-purpose output
only.
● 3 of these 32 pins (P0.24, P0.26 and P0.27) are reserved. Hence, they
are not available for use. Also, these pins are not mentioned in pin
diagram.
PORT1 is also a 32-bit port. Only 16 of these 32 pins (P1.16 – P1.31) are
available for use as general-purpose input or output.
Slow and Fast GPIO Registers
LED
The intensity of the light emitted by an LED depends on the amount of
forward current passed through the device. The maximum allowable forward
current is denoted by IFmax.
When designing an LED circuit, we have to know the typical voltage drop,
VTyp across the device, and the maximum allowable voltage drop, VFmax.
The brightness of the emitted light is measured in millicandela (mcd) and this
is usually referenced to the forward current.
For example, standard red LEDs are quoted to have brightness of 5 mcd when
operated at 10 mA.
Interfacing LED
● Current passing through the LED should be limited to maximum
forward current (IF).
● To find the value of this resistor, we use the forward voltage and
forward current.
We design a circuit with 5V supply and forward current of 10mA.
We use a red LED here.
P0.28
P0.28
P0.29
/* Keypad Connection:
P0.2,P0.3,P0.4,P0.5 ---Col---Read Lines
P0.6,P0.7,P0.8,P0.9 ---Row---Scan Lines
LCD:
RS---P0.28
EN---P0.29
Data--P1.16 to P1.23 */
Embedded C program for the Interfacing keypad and LCD
#include<lpc21xx.h>
void lcdcmd(unsigned int); IO0PIN=0x00000380; // First Scan
void lcddata(unsigned int); Line(row)
void delay_lcd(void); if(( IO0PIN & 0x0000003c )!= 0x0000003c))
int main(void) {
{ switch(IO0PIN & 0x0000003c)
while(1) {
{ case 0x00000038 : lcddata("C");break;
IODIR1=0x00ff0000; case 0x00000034 : lcddata("D");break;
IODIR0=0x300003c0; case 0x0000002c : lcddata("E");break;
lcdcmd(0x38); case 0x0000001c : lcddata("F");break;
lcdcmd(0x0e); }
lcdcmd(0x01); }
lcdcmd(0x06);
lcdcmd(0x83);
lcdcmd(0xC0);
IO0PIN=0x00000340;// Second Scan Line(row)
IO0PIN=0x000001c0; // Four Scan Line(row)
if(( IO0PIN & 0x0000003c )!= 0x0000003c) )
if(( IO0PIN & 0x0000003c )!= 0x0000003c)
{
{
switch(IO0PIN & 0x0000003c)
switch(IO0PIN & 0x0000003c)
{
{
case 0x00000038 : lcddata("8");break;
case 0x00000038 : lcddata("0");break;
case 0x00000034 : lcddata("9");break;
case 0x00000034 : lcddata("1");break;
case 0x0000002c : lcddata("A");break;
case 0x0000002c : lcddata("2");break;
case 0x0000001c : lcddata("B");break;
case 0x0000001c : lcddata("3");break;
}
}
}
}
IO0PIN=0x000002c0;// Third Scan Line(row)
delay_lcd();
if(( IO0PIN & 0x0000003c )!= 0x0000003c)
}
{
}
switch(IO0PIN & 0x0000003c)
{
case 0x00000038 : lcddata("4");break;
case 0x00000034 : lcddata("5");break;
case 0x0000002c : lcddata("6");break;
case 0x0000001c : lcddata("7");break;
}
}
void lcdcmd(unsigned int cmddata)
{ void delay_lcd(void)
IOCLR1=0x00ff0000; {
IOCLR0=0x10000000; int j;
cmddata=cmddata<<16; for(j=0;j<10000;j++);
IOSET1=cmddata; return;
IOSET0=0x20000000; }
delay_lcd();
IOCLR0=0x20000000;
delay_lcd();
return;
}
void lcddata(unsigned int outdata)
{
IOCLR1=0x00ff0000;
IOSET0=0x10000000;
outdata=outdata<<16;
IOSET1=outdata;
IOSET0=0x20000000;
delay_lcd();
IOCLR0=0x20000000;
delay_lcd();
return;
Graphics LCD
Graphics LCD
Internal block diagram of a KS0108B (NT7108C) based 128x64 pixel GLCD module
➢ The NT1707C drives the 64 display lines, COM1 – COM64.
➢ The first NT7108C drives the left half segments (SEG1 to
SEG64) and the second one drives the right half segments
(SEG65 to SEG128) of the display.
➢ The two halves of the display can be individually accessed
through the chip select pins (CS1 and CS2) of the two
NT7108C drivers.
➢ Each half consists of 8 horizontal pages (0-7) which are 8 bits
(1 byte) high. This is illustrated in the drawing below.
Structure of the GLCD
GLCD display coordinates
Pin description of Winstar WDG01510 GLCD module
Display control instructions
Data print on GLCD
Interfacing a KS0108 based Graphics LCD
Displaying Image
We can display binary image up to 128x64 pixel resolution.
Binary image means each pixel has only two values i.e. 0 or 1.
- GLCD 128x64 JHD12864E can display only Binary image.
- So, we need to convert image into binary format
- There are several ways to do this, we will use Image2GLCD application.
- Image2GLCD application converts JPG, GIF, BMP, PNG format image
files to binary format.
Outline:
1. Interrupt structure of LPC2148
2. Interfacing with LED, LCD
3. Interfacing with KEYPAD, GLCD
4. Simple LPC2148 GPIO Programming examples Using timers of
LPC2148 to generate delay
5. Serial communication programming for transmission and
reception from computer
6. Programming for UART
Timers in LPC2148 ARM7 Microcontroller
● The LPC2148 has two functionally identical general purpose
timers: Timer0 and Timer1.
● These both timers are 32-bit along with 32-bit prescaler.
● Timer allows us to generate precise time delay.
Since we’re transferring at 9600 bps, the time spent holding each
of those bits high or low is 1/(9600 bps) or 104 µs per bit.
Wiring and Hardware
A serial bus consists of just two wires - one for sending data and
another for receiving. As such, serial devices should have two
serial pins: the receiver, RX, and the transmitter, TX.
Hardware Implementation
RS-232, which can be found on some of the more ancient
computers and peripherals, is like TTL serial flipped on its head.
RS-232 signals usually range between -13V and 13V, though the
spec allows for anything from +/- 3V to +/- 25V.
On these signals a low voltage (-5V, -13V, etc.) indicates either
the idle line, a stop bit, or a data bit of value 1.
A high RS-232 signal means either a start bit, or a 0-value data
bit. That’s kind of the opposite of TTL serial.
The MAX232 is an IC originally designed by a company called
Maxim IC that converts the +/-13V(+/-25V) signals of RS232
down to the 0/5V signals that our Microcontroller can understand.
It also boosts the voltage of our Microcontroller to the needed +/-
13V(+/-25V) of the RS232 protocol so that a computer can
understand our Microcontroller and vice versa.
UART section of LPC 2148:
● The LPC 2148 contains two UARTs which are compatible with
UART IC 16C550 (Industry Standard UART IC).
● UART0 provides only standard transmit and receive data lines
● UART1 also provides a full modem control handshake interface
along with standard transmit and receive data lines.
LPC214x UART0
Features:
● 16 byte Receive and Transmit FIFOs
● Register locations conform to ‘550 industry standard.
● Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
● Built-in fractional baud rate generator with autobauding
capabilities.
● Mechanism that enables software and hardware flow control
implementation.
UART0 block diagram
LPC214x UART1
Features
● UART1 is identical to UART0, with the addition of a modem
interface.
● 16 byte Receive and Transmit FIFOs.
● Register locations conform to ‘550 industry standard.
● Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
● Built-in fractional baud rate generator with autobauding capabilities.
● Mechanism that enables software and hardware flow control
implementation.
● Standard modem interface signals included with flow control (auto-
CTS/RTS) fully supported in hardware (LPC2144/6/8 only).
UART1 block diagram
The master formula for calculating baud rate is given as :
#include<LPC21xx.h>
void main()
{
char a;
PINSEL0=0x00000005;//P0.0 as TxD0 & P0.1 as RxD0
U0LCR=0x83;//8 -bit character length,DLAB=1
U0DLM=0x00;//
U0DLL=0x61;// Baud rate=9600
U0LCR=0x03;// DLAB=0; to load baud rate value
while(1)
{
while(!(U0LSR&0x01)); //monitoring TI flag
a=U0RBR;