Normalized Polish Expression

 Wong and Liu presented a method named Normalized

Polish Expression [Wong and Liu, 1986] to represent
slicing floorplans, using the method of simulated
annealing.

 Given a binary tree that represents a slicing floorplan of n

blocks, the polish expression of this tree is a string of
length 2n − 1 that consists of the block numbers and H
(for horizontal cut) and V (for vertical cut). The numbers
in the expression are called operands, and the H and V are
called operators.

Practical Problems in VLSI Physical Design Polish Expression (1/8)

 Simulated Annealing

© KLMH
Introduction

 Simulated Annealing (SA) algorithms are probabilistic and iterative in nature.

 Begins with an initial (arbitrary) solution and seeks to incrementally improve

the objective function.

 During each iteration, a local neighborhood of the current solution is considered. A

new candidate solution is formed by a small perturbation of
the current solution.

 Unlike greedy algorithms, SA algorithms can accept candidate solutions with higher
cost.

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VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 2
 Simulated Annealing

© KLMH
Cost
Initial solution

Local
optimum Global
optimum

Solution states

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VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 3
 Simulated Annealing

© KLMH
What is annealing?

 Definition (from material science): controlled cooling process of high-temperature

materials to modify their properties.
 Cooling changes material structure from being highly randomized (chaotic) to being
structured (stable).
 The way that atoms settle in low-temperature state is probabilistic in nature.

 Slower cooling has a higher probability of achieving a perfect lattice with minimum-
energy
 Cooling process occurs in steps
 Atoms need enough time to try different structures
 Sometimes, atoms may move across larger distances and create (intermediate) higher-
energy states
 Probability of the accepting higher-energy states decreases with temperature

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VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 4
 Simulated Annealing

© KLMH
Simulated Annealing

 Generate an initial solution and evaluate its cost

 Generate a new solution by performing a random walk
 Solution is accepted or rejected based on a temperature parameter T
 Higher T indicates higher probability to accept a solution with higher cost
 T slowly decreases to form the finalized solution.

 Boltzmann acceptance criterion:

currsol : current solution
nextsol: new solution after perturbation
T: current temperature
r: random number between[0,1) from normal distr.

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VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 5
 Simulated Annealing – Algorithm

© KLMH

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VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 6
 Simulated Annealing – Algorithm

© KLMH
Input: initial solution init_sol
Output: optimized new solution curr_sol

T = T0 // initialization
i=0
curr_sol = init_sol
curr_cost = COST(curr_sol)
while (T > Tmin)
while (stopping criterion is not met)
i=i+1
(ai,bi) = SELECT_PAIR(curr_sol) // select two objects to perturb
trial_sol = TRY_MOVE(ai,bi) // try small local change
trial_cost = COST(trial_sol)
cost = trial_cost – curr_cost
if (cost < 0) // if there is improvement,
curr_cost = trial_cost // update the cost and
curr_sol = MOVE(ai,bi) // execute the move
else

© 2011 Springer Verlag

r = RANDOM(0,1) // random number [0,1]
if (r < e –Δcost/T) // if it meets threshold,
curr_cost = trial_cost // update the cost and
curr_sol = MOVE(ai,bi) // execute the move
T=α∙T // 0 < α < 1, T reduction

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VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 3: Chip Planning 7
 The authors showed that the normalized polish expression
corresponds to the post-order traversal of the slicing tree and
satisfies the following properties:
(i) each block appears exactly once in the string,
Example PE: P1 = 25V1H374VH6V8VH

(ii) the number of operands is larger than the number of

operators at all positions in the string, which is called the
“balloting property” in the paper, and

(iii) there are no consecutive operators of the same type in the

string, which is called the “normality property.” This
normalized polish expression has 1-to-1 correspondence to
a slicing floorplan so that we can obtain a unique slicing
floorplan from a normalized polish expression, vice-versa.
Practical Problems in VLSI Physical Design Polish Expression (8/8)
 We can easily perturb the current slicing floorplanning
solution to obtain a new neighbouring solution. The authors
provided three kinds of “moves” to perturb the normalized
polish expression so that the resulting expression remains
normalized and satisfies the balloting property.

 we can quickly evaluate the quality of the given polish

expression, which is done by computing the location of the
blocks in the floorplan with a O(n log n) bottom-up traversal
of the corresponding slicing tree. We can then obtain the area
of the floorplan as well as the total wire length.

Practical Problems in VLSI Physical Design Polish Expression (9/8)

 A new algorithm for floorplan design using the method of
simulated annealing.
 The major contributions of the paper are [1]:
1. A new representation of floorplans (normalized Polish
expressions) which enables us to carry out the neighbourhood
search effectively.
2. A simultaneous minimization of area and total
interconnection length in the final solution. Experimental
results indicate that the algorithm performs well in many test
problems.

Practical Problems in VLSI Physical Design Polish Expression (10/8)

 Procedure
 We define three types of moves that can be used to modify a
given normalized Polish expression.
Ml. Swap two adjacent operands.
M2. Complement some chain of nonzero length.
M3. Swap two adjacent operand and operator.

Two normalized Polish expressions are said to be neighbours if

one can be obtained from the other via one of these three moves.

Practical Problems in VLSI Physical Design Polish Expression (11/8)

Normalized Polish Expression
 Draw slicing floorplan based on:
 Initial PE: P1 = 25V1H374VH6V8VH
 Dimensions: (2,4), (1,3), (3,3), (3,5), (3,2), (5,3), (1,2), (2,4)
Rotation is not allowed and place the lower left corner of each
block to the lower left corner of its room.
H (Y-axis)

Initial floorplan

W (X-axis)
Area = 11 x 15 unit2

Practical Problems in VLSI Physical Design Polish Expression (12/8)

M1 Move
 Swap module 3 and 7 in P1 = 25V1H374VH6V8VH
 We get: P2 = 25V1H734VH6V8VH
 Area changed from 11 × 15 to 13 × 14

Practical Problems in VLSI Physical Design Polish Expression (13/8)

 Change on Floorplan

Area = 11 x 15 Area = 13 x 14

Practical Problems in VLSI Physical Design Polish Expression (14/8)

M2 Move
 Complement last chain in P2 = 25V1H734VH6V8VH
 We get: P3 = 25V1H734VH6V8HV
 Area changed from 13 × 14 to 15 × 11

Practical Problems in VLSI Physical Design Polish Expression (15/8)

 Change on Floorplan

Area = 13 x 14 Area = 15 x 11

Practical Problems in VLSI Physical Design Polish Expression (16/8)

M3 Move
 Swaps 6 and V in P3 = 25V1H734VH6V8HV
 We get: P4 = 25V1H734VHV68HV
 Area changed from 15 × 11 to 15 × 7

Practical Problems in VLSI Physical Design Polish Expression (17/8)

 Change on Floorplan

Area = 15 x 11 Area = 15 x 7

Practical Problems in VLSI Physical Design Polish Expression (18/8)

Initial Temperature Calculation

In general, better results are produced with a high initial temperature and a slow
rate of cooling, at the cost of increased runtime.
Practical Problems in VLSI Physical Design Polish Expression (19/8)
References
 “A NEW ALGORITHM FOR FLOORPLAN DESIGN”
by D. F. Wong and C. L. Liu, 1986.
 “Practical problems in VLSI physical design” by Sung
Kyu Lim (Book).
 “VLSI physical design: from graph partitioning to timing
closure” by Kahng et al.

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