1.

MOSFET introduction
2.Physical operation
3.Layout introduction
1.MOSFET introduction
The metal-oxide-semiconductor field- effect transistor (MOSFET) is a type of transistor used for
amplifying or switching electronic signals. And it has four terminals as follow :

S : source
G :gate
D :drain
B : body (well or substrate) or bulk
 There are two kind of MOSFET : NMOS and PMOS.

 The gate is separated from the n channel by a layer of insulating silicon dioxide (the O
in MOSFET, for oxide). Therefore, it does not make electrical contact with the rest of
the semiconducting material.
 The source is so named because it is the source of the charge carriers (electrons for nchannel,
holes for p-channel) that flow through the channel. Similarly, the drain is
where the charge carriers leave the channel
2. Physical operation ( for NMOS)

 when 𝑉𝐺𝑆 < 0 mobile holes from the substrate are attracted (or accumulated) under the
gate oxide. Therefore, there is no current. The transistor is OFF.
 When 𝑉𝑡ℎ > 𝑉𝐺𝑆 , it is not positive enough to
attract a large number of electrons, the
surface under the gate is said to be nearly
depleted (depleted of free electrons and
holes).

 In reality, there is still a current with very small

value and it is called subthreshold current.
The NMOS operated in this region is said to be
in weak inversion or the subthreshold region.
 When 𝑉𝐺𝑆 is sufficiently large (>> 𝑉𝑡ℎ ) so that a large number of electrons are attracted
under the gate. And a small positive voltage is applied to the Drain, there will be a
current 𝐼𝐷 passing from Drain to Source. The transistor is ON.

• Moreover, under the 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑡ℎ condition the greater the 𝑉𝐷𝑆 is, the higher the 𝐼𝐷
is. This region is called triode region

 If 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑡ℎ = VDS.sat,

NMOS is in the saturation region

Saturation point.
More information in
• (29 -9 to 29 -10 ) physics for scientists & engineers
• (5.3 ) CMOS_Circuit_Design_Layout_and_Simulation
3. Layout introduction
Layout of inv
A
GND VDD
Y

p+ n+ n+ p+ p+ n+
n well
p substrate

substrate tap well tap

Layer pp cover
diffusion of p+ VDD
P substrate

Well
I OUT
N

Layer np cover VSS

diffusion of n+
Layout of NAND

NAND 1 finger NAND 2 finger

Pratice: sketch schematic from layout

A2
OUT

A1
Floor -plan

 Try to share diffusion as much as possible to save area. ( hahahaha :v )

Pratice : sketch 3 different stick diagram form schematic

SE

IN

SEX OUT