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INTRODUCTION

• The advancement in modern technology is only possible due to


compressing the size of basic component.
• These basic components are classified into different categories
on the basis of there basic parameters.
• These categorization is collectively named as logic families.
• Getting the knowledge about the logic family, will enable us to in
the selection of suitable component to our circuitry.
LOGIC FAMILIES
UNIPOLAR BIPOLAR
CHARACTRIZATION OF LOGIC FAMILIES
P-MOS N-MOS CMOS SATURATED UNSATURATED

SHOTKEY
RTL DCTL 𝐼2 L DTL HTL TTL ECL
TTL
PARAMETERS
• Noise Margin:
• Noise Immunity
• Propagation Delay
• Power Dissipation
• Figure OF Merit
• Fan In
• Fan Out
RESISTER TRANSISTOR LOGIC (RTL)
Vcc

Parameters Value A B Vout


Vout

NOISE MARGIN POOR 0 0 1

FAN OUT 4
0 1 0
PROPAGATION 12
DELAY
(ns) 1 0 0
POWER 12
DESSIPATION 1 1 0
(mW)
A B
FIGURE OF MERIT 144
(pJ)
DIRECT-COUPLED TRANSISTOR
LOGIC (DCTL)
Vcc
Parameters Value A B Vout
Vout

NOISE MARGIN POOR 0 0 1

FAN OUT 4
0 1 0
PROPAGATION 10
DELAY
(ns) 1 0 0
POWER 30
DESSIPATION 1 1 0
(mW)
A B
FIGURE OF MERIT 300
(pJ)
INTEGRATED INJECTION LOGIC 𝟐
(𝑰 𝑳)
• Construction only using BJT’s.
• Uses multi collector transistors
• NPN are powered from pnp
• Due to no use of resistor the circuit is compact and
there for it is used in IC-fabrication
INTEGRATED INJECTION LOGIC 𝟐
(𝑰 𝑳)
Parameters Value Vcc A B Vout

NOISE MARGIN HIGH 0 0 1

FAN OUT 8-11


0 1 0
PROPAGATION 25-2500
DELAY Vout
(ns) 1 0 0
POWER 5-25
DESSIPATION 1 1 0
(mW)
FIGURE OF MERIT 4
(pJ) A B
DIODE TRANSISTOR LOGIC (DTL)
Parameters Value A B Vout
Vcc

NOISE MARGIN HIGH


0 0 1

FAN OUT 8 A
Vout

0 1 0
PROPAGATION 30
DELAY
(ns) 1 0 0
B

POWER 8-12
DESSIPATION 1 1 0
(mW)
FIGURE OF MERIT 300
(pJ)
DIODE TRANSISTOR LOGIC (DTL)
Parameters Value + Vcc A B Vout

NOISE MARGIN HIGH 0 0 1

FAN OUT 8
0 1 1
PROPAGATION 30
Vout
DELAY
(ns) A 1 0 1
POWER 8-12
DESSIPATION B 1 1 0
(mW)
- VBB
FIGURE OF MERIT 300
(pJ)
HIGH THERSHOLD LOGIC (HTL)
• It is the variation of DTL.
• Specially designed for high noise environment like industries.
• We use Zener to set large offset between logic 1 & logic 0 at
voltage level.
• Advantage: Increased noise margin, high noise threshold
value.
• Disadvantage: Slow speed , high power drain.
HIGH THERSHOLD LOGIC (HTL)
Vcc=15V A B Vout

0 0 1

0 1 1

A Vout 1 0 1

B
6.9 V
1 1 0
TRANSISTOR TRANSISTOR LOGIC
Parameters Value
(TTL) A B C Vout

NOISE MARGIN MEDIUM Vcc


0 0 0 1
Vout

FAN OUT 10
0 0 1 1
PROPAGATION 10
DELAY
(ns) 0 1 0 1
POWER 10
A
DESSIPATION B 0 1 1 1
C
(mW)
FIGURE OF MERIT 100 . . . .
(pJ) . . . .
. . . .
1 1 1 0
UNIPOLAR LOGIC FAMILIES

• N-MOS : Output is taken across drain terminal.


• P-MOS : Output is taken across source terminal.
NOR GATE USING P-MOS
VDD
A B Vout
D
A
0 0 1

0 1 0

1 0 0

B
1 1 0

Vout
GND
NOR GATE USING N-MOS
A B Vout
Vcc
0 0 1

Vout
0 1 0
D
B A
1 0 0

1 1 0
S

GND
CMOS NOR GATE
Parameters Value A B Vout

NOISE MARGIN HIGH 0 0 1

FAN OUT 50
0 1 1
PROPAGATION 70
DELAY
(ns) 1 0 1
POWER 0.1
DESSIPATION 1 1 0
(mW)
FIGURE OF MERIT 7
(pJ)
COMPRISON
PARAMETERS LOGIC FAMILY
RTL DCTL 𝐼2L DTL TTL CMOS
(P-MOS &
NMOS)
NOISE MARGIN POOR POOR HIGH HIGH MEDIUM HIGH

FAN OUT 4 4 8-11 8 10 50


PROPAGATION 12 10 25-2500 30 10 70
DELAY
(ns)
POWER 12 30 5-25 8-12 10 0.1
DESSIPATION
(mW)
FIGURE OF MERIT 144 300 4 300 100 7
(pJ)