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Lecture1
Instruction Set Architecture
PC 21
MAR 501
500
21
MBR LOAD
STOR
M(X)
M(500),
500,
43 ADD
(Other
M(X)
Ins) 501
IR LOAD
STOR
ADD M(X)M(X)
IBR ADD
(Other
M(X) Ins)
501
AC 37
Add 501
IBR
M(X) PC =PC12
PC←=
Mar
MAR ←PC
LOAD M(X) 500, 3
ADD M(X) 501
4
STOR M(X) 500, (Other Ins)
IR MAR
MARadd== 2
MAR 501
MAR==500
=500
1
501
add == 500
add
add =12
IAS Computer AC MQ
MARPC
MBRM[MAR] Arithmetic & Logic Circuits
Input/output
IBRMBR<20..39> IBRMBR<20..39> Equipments
IRMBR<0..7> IRMBR<0..7>
MARMBR<8..19> MARMBR<8..19> MBR
MBRM[MAR] MBRAC
ACMBR M[MAR}MBR
IRIBR<0..7> IRIBR<0..7>
MARIBR<8..19> IBR PC
MBRM[MAR]
ACAC + MBR Main
PCPC+1 Memory
MARPC
IR
MBRM[MAR] MAR
Control
Circuits
Register transfer operation for
addition operation