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Basic Features
II: Atmega8 – Basic features
ATmega8 - RISC Architecture
Power down mode: Saves the register contents but freezes the Oscillator,
disabling all other chip functions until the next Interrupt or Hardware Reset.
ADC Noise Reduction mode: Stops the CPU and all I/O modules except
asynchronous timer and ADC, to minimize switching noise during ADC
conversions.
Operating Voltages
● 2.7 - 5.5V (ATmega8L)
● 4.5 - 5.5V (ATmega8)
Speed Grades
● 0 - 8 MHz (ATmega8L)
● 0 - 16 MHz (ATmega8)
Harvard architecture
Memory organization
II: Atmega8 – Basic features
EEPROM - Memory:
Lower 1120 Data memory locations address the Register File, the I/O
Memory, and the internal data SRAM (First 96 locations address the
Register File and I/O Memory, Next 1024 locations address the internal
data SRAM).
I/O Ports
II: Atmega8 – Basic features
● General Purpose IO : Data Direction Input or Output
● Internal Pullup can be used for Input Pins
● Output driver can source 20mA current
● protection diodes to GND and VCC
• 3 I/O-Registers for each port:
Data Register (r/w): PORTB, PORTC, PORTD (read/write)
Data Direction Register (r/w): DDRB, DDRC, DDRD (read/write)
Port Input Pin Register (r): PINB, PINC, PIND (read)
PORTx: logic one - pin is configured as an input pin: pull-up resistor activated
logic zero – pin is configured as an output pin: pull-up resistor off
pins are tri-stated when a reset condition becomes active
PINx: port pin can be read through the PINxn Register Bit
Timers / Counters
8-bit Timer/Counter0
Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter
module. The main features are:
• Single Channel Counter
• Frequency Generator
• External Event Counter
• 10-bit Clock Prescaler
Associated Registers
TOIE0: this bit when sets to “1” enables the OVERFLOW interrupt
Timer/Counter Control Register – TCCR0
Timer/Counter Register – TCNT0
Flash an LED every 6 ms and CPU clock frequency of 32 kHz using Timer0.
= [6 ms / (1/32kHz)] – 1 = 191
= [8 ms / (1/16MHz)] – 1 = 1,27,999
}
Problem Statement 3:
At a frequency of 62.5 kHz (prescaler = 256), each tick takes 0.016 ms.
Thus to achieve a delay of 0.848 ms, it would require 53 ticks.
Thus, in the 13th iteration, we only allow the timer to count up to 53, and
then reset it.
TCNT0 (Timer/Counter Register ) = 0 x 00; //Initalization
void pin_config()
{
DDRC = 0x02; // connect led to pin PC1
PORTC=0x00; // Intilaize
}
void timer0_init()
{
TCCR0 = 0x04; // set up timer with prescaler = 256
TCNT0 = 0x00; // initialize counter
TIMSK = 0x01; // enable overflow interrupt
sei(); // enable global interrupts
tot_overflow = 0; // initialize overflow counter variable
}
// TIMER0 overflow interrupt service routine
// called whenever TCNT0 overflows
ISR(TIMER0_OVF_vect)
{
tot_overflow++; // keep a track of number of overflows
}
int main(void)
{
pin_config();
timer0_init();
while(1)
{
if (tot_overflow >= 12)
{
if (TCNT0 >= 53)
{
PORTC ^= (1 << 1); // toggles the led
TCNT0 = 0; // reset counter
tot_overflow = 0; // reset overflow counter
}
}
}
}
II: Atmega8 – Basic features
Analog Comparator
ACME : Analog Comparator Multiplexer Enable
ACD : Analog Comparator Disable
ACBG : Analog Comparator Bandgap Select
ACO : Analog Comparator Output
ACI : Analog Comparator Interrupt Flag
ACIE : Analog Comparator Interrupt Enable
ACIC : Analog Comparator Input Capture Enable
ACIS1, ACIS0 : Analog Comparator Interrupt Mode Select
The Analog Comparator compares the input values on the positive pin
AIN0 and negative pin AIN1.
When the voltage on the positive pin AIN0 is higher than the voltage
on the negative pin AIN1, the Analog Comparator Output, ACO, is set.
When this bit is written logic one and the ADC is switched off
(ADEN in ADCSRA is zero), the ADC multiplexer selects the
negative input to the Analog Comparator.
When changing the ACD bit, the Analog Comparator Interrupt must be disabled by
clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
When this bit is cleared, AIN0 is applied to the positive input of the Analog
Comparator.
Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly
connected to ACO. The synchronization introduces a delay of 1 - 2 clock
cycles.
The Analog Comparator Interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set.
The SPI Master initiates the communication cycle when pulling low the Slave Select
SS pin of the desired Slave.
Master and Slave prepare the data to be sent in their respective Shift Registers, and
the Master generates the required clock pulses on the SCK line to interchange data.
Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI,
line, and from Slave to Master on the Master In – Slave Out, MISO, line.
After each data packet, the Master will synchronize the Slave by pulling high the
Slave Select, SS, line.
When configured as a Master:
When this is done, writing a byte to the SPI Data Register starts the
SPI clock generator, and the hardware shifts the eight bits into the
Slave.
After shifting one byte, the SPI clock generator stops, setting the end
of Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in
the SPCR Register is set, an interrupt is requested.
The Master may continue to shift the next byte by writing it into
SPDR, or signal the end of packet by pulling high the Slave Select,
SS line.
The last incoming byte will be kept in the Buffer Register for later
use.
When configured as a Slave:
SPI interface will remain sleeping with MISO tri-stated as long as the
SS pin is driven high.
In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming
clock pulses on the SCK pin until the SS pin is driven low.
The Slave may continue to place new data to be sent into SPDR
before reading the incoming data.
The last incoming byte will be kept in the Buffer Register for later
use.
SPI Control Register – SPCR
When the DORD bit is written to zero, the MSB of the data word is
transmitted first.
Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode
when written logic zero.
The user will then have to set MSTR to re-enable SPI Master mode.
If SS is an input and is driven low when the SPI is in Master mode, this will
also set the SPIF Flag.
Alternatively, the SPIF bit is cleared by first reading the SPI Status Register
with SPIF set, then accessing the SPI Data Register (SPDR).
Bit 6 – WCOL: Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a
data transfer.
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status
Register with WCOL set, and then accessing the SPI Data Register.
When the SPI is configured as Slave, the SPI is only guaranteed to work at
fosc/4 or lower. The SPI interface on the ATmega8 is also used for Program
memory and EEPROM downloading or uploading.
SPI Data Register – SPDR
The SPI Data Register is a Read/Write Register used for data transfer
between the Register File and the SPI Shift Register. Writing to the
register initiates data transmission. Reading the register causes the Shift
Register Receive buffer to be read.
Data Modes
There are four combinations of SCK phase and polarity with respect to
serial data, which are determined by control bits CPHA and CPOL.
Data bits are shifted out and latched in on opposite edges of the SCK
signal, ensuring sufficient time for data signals to stabilize.
II: Atmega8 – Basic features
Set SREG I-bit and the corresponding interrupt mask in the GICR
MCU Control Register – MCUCR
The flag is cleared when the interrupt routine is executed. Alternatively, the
flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 and INT0 are configured as a level interrupt.
OPERATION 1 : A roll action is perform using the LEDs. The first LED is lit
and roll down to the last LED then back to the first LED. This operation is
done continuous.
void pin_config()
{
DDRD = 1<<PD2; // Set PD2 as input (Using for interupt INT0)
PORTD = 1<<PD2; // Enable PD2 pull-up resistor
while(1)
{
if(PORTB >= 0x80)
PORTB = 0x01;
else
PORTB = PORTB << 1; // Shift to the left
_delay_ms(100);
}
}
USART
(Universal Synchronous / Asynchronous
Receiver / Transmitter)
USART interface
Full Duplex Operation (Independent Serial Receive and Transmit
Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Databits and 1 or 2
Stop Bits
Odd or Even Parity Generation and Parity Check Supported by
Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low
Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register
Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
How to set up USART:
The first step is to set the baud rate in both, the master and the
slave. The baud rate has to be the same for both – master and
slave.
Set the number of data bits, which needs to be sent.
Get the buffer ready! In case of transmission (from AVR to some
other device), load it up with the data to be sent, whereas in case
of reception, save the previous data so that the new received
data can be overwritten onto it.
Then enable the transmitter/receiver according to the desired
usage.
UDR: USART I/O Data
Register
Modes of Operation
Write one to ADLAR to left adjust the result. Otherwise, the result is right
adjusted.
Bits 3:0 – MUX3:0: Analog Channel Selection Bits
ADC Control and Status Register A – ADCSRA
Bits 2:0 –
ADPS2:0:
ADC Prescaler
Select Bits
The ADC Data Register – ADCL and ADCH
With regards to Atmega8 a few concepts to know beforehand are:
AVCC: This AVR pin supplies power to ADC. AVcc must not differ more than ± 0.3V from
Vcc
AREF: Another AVR pin which can optionally be used as an external voltage reference pin.
Voltage Resolution: This is the smallest voltage increment which can be measured. For 10
bit ADC, there can be 1024 different voltages and for 8 bit ADC, there can be 256 different
voltages.
Input voltage can be measured as: VIn [V] = (ADCH*256+ADCL) * VRef [V] / 1024 for 10
bit ADC
Input voltage can be measured as: VIn [V] = (ADCH)* VRef [V]/256 for 8 bit ADC
Hardware units like DAC (Digital to Analog converter), Comparator, SHA or S/H (Signal and
Hold), SAR (Successive approximation register) together complete AD conversion.
Most AVR microcontrollers have built in ADC which reduces cost and space for an external
ADC
Lastly, be informed that all ADC pins are connected to only one internal ADC, which means
you need to do one conversion at a time.
E.g.:- Switch ON and OFF two LED’s based on the ADC result
void adc_int()
{
ADCSRA=0x85;
ADMUX=0x05;
}
int main (void)
{
pin_config ();
adc_int();
while(1)
{
unsigned int adc_value; // Variable to hold ADC result
ADCSRA=0xC5; // Start conversion
while (ADSC==0); // wait until conversion completes;
adc_value = ADCW;//Store ADC result (ADCW means stores values of ADCL and ADCH)