FPGA

(FIELD PROGRAMMABLE GATE

ARRAY)

Presented by :
Subin Mathew
RASET
Cochin
HISTORY
Programmable Read Only Memory (PROM)
 fuse programming
 n- address i/p can implement n i/p logic fun.

Problem:
 Area efficiency.

Programmable Logic Array (PLA)

 Programmable AND plane followed by
programmable or wired OR plane.
 Sum of product form

Problem :
 Two level programming adds delay
NEXT -
Programmable Array Logic (PAL)
 Programmable AND plane and fixed OR plane.

 Flexible comparably.

All these PLA and PAL are Simple Programmable

Logic Devices (SPLD).
Problem:
 Logic plane structure grows rapidly with number of
inputs
NEXT -
To mitigate the problem
Complex Programmable Logic Devices (CPLD)
 programmably interconnect multiple SPLDs.

Problem :
 Extending to higher density difficult
 Less flexibility
COMPARISON
FPGA
A Field Programmable Gate Array (FPGA) is a
Programmable Logic Device(PLD) with higher
densities and capable of implementing different
functions in a short period of time.

Topics covered:-
• FPGA Overview
• Logic Block
• FPGA Routing Techniques
• Programming Methodology
• FPGA Design Flow
FPGA OVERVIEW
 2-D array of logic blocks and flip-flops with
programmable interconnections.
 Compact design

 User can configure

 Intersectionsbetween the logic blocks
 The function of each block
Why do we need FPGAs?

WORLD OF INTEGRATED CIRCUITS

Full-Custom Semi-Custom User

ASICs ASICs Programmable

PLD FPGA
WHICH WAY TO GO?

ASICs FPGAs

High performance Low development cost

Low power Short time to market

Low cost in
high volumes Reprogrammable
OTHER FPGA ADVANTAGES

 Manufacturing cycle for ASIC is very costly, lengthy

and engages lots of manpower
 Mistakes not detected at design time have large
impact on development time and cost
 FPGAs are perfect for rapid prototyping of digital
circuits
 Easy upgrades like in case of software

 Unique applications
LOGIC BLOCKS
 Purpose: to implement combinational and sequential
logic functions.
 Logic blocks can be implemented by:-

• Transistor pairs
• Multiplexers
• Look up tables( LUT)
• Wide fan-in AND-OR structure.
Granularity: is the hardware abstraction level.
According to granularity, two types of Blocks :
 Fine Grain Logic Blocks

 Coarse Grain Logic Blocks

 FINE GRAIN

1. The Cross Point

FPGA

 Transistors are
interconnected.
 Logic block is
implemented using
transistor pair tiles.
2. Plessey FPGA :-
• 2-input NAND gate forms basic building block
• Static RAM programming technology
FINE GRAIN
Advantage:
 Blocks are fully utilized.

Disadvantage:
 Require large numbers of wire segments and
programmable switches.
 Need more area.
COARSE GRAIN LOGIC BLOCKS
 Many types exists according to implementations
 Multiplexer Based and Look-up-Table Based are most
common

1. The Xilinx Logic Block:

 A SRAM function as a LUT.
 Address line of SRAM as input
 Output of SRAM gives the logic output
 k-input logic function =2^k size SRAM
 K-i/p LUT gives 2^2^k logic functions
Advantage:
 High functionality
 k inputs logic block can be implemented in no. of ways

Disadvantage:
 Large no of memory cells required if i/p is large
2. Altera logic block:-
 Wide fan-in
 Up to 100 i/p AND gate fed into OR gate with 3-8 i/ps
Advantage:-
 Few logic block can implement the entire functionality
 Less area required

Disadvantage:-
 If i/psare less, usage density of block will be low
 Pull up devices consume static power
EFFECTS OF GRANULARITY ON FPGA DENSITY
AND PERFORMANCE
Tradeoff
 Granularity increase -> Blocks less

 More Functional Blocks-> more area

Area is normally measured by total number of bits

needed to implement the design. So look the
example
EXAMPLE
FPGA ROUTING TECHNIQUES

 Comprises of programmable switches and wires

 Provides connection between I/O blocks, logic blocks etc.
 Routing decides logic block density and area consumed

Different routing techniques are:-

 Xilinx Routing architecture
 Actel routing methodology
 Altera routing methodology
Xilinx Routing architecture
 connections are made through a connection block.
 SRAM is used to implement LUT. So connection sites are large
 Pass transistors for connecting output pins
 multiplexers for input pins.
 wire segments used are:-
 general purpose segments
 Direct interconnect
 long line
 clock lines
Actel routing methodology
 more wire segments in horizontal direction.

 i/p & o/p vertical tracks can make connection with

every horizontal track.
 Routing is flexible.

 Drawback:-

more switches are required => more capacitive load.

Altera routing methodology

 It has two level hierarchy.

 first level => 16 or 32 of the logic
blocks are grouped into a Logic Array Block(LAB)
 connections are formed using EPROM
 Second level=> LABs are interconnected using
Programmable Interconnect Array(PIA)
PROGRAMMING METHODOLOGY

 Electrically programmable switches are used to program

FPGA
 Properties of programmable switch determine on-
resistance, parasitic capacitance, volatility,
reprogrammability, size etc.
 Various programming techniques are:-
 SRAM programming technology
 Floating Gate Programming
 Antifuse programming methodology
SRAM programming technology
 Use Static RAM cells to control pass gates or multiplexers.
 1= closed switch connection
0= open
 For mux, SRAM determines the mux input selection
process.

Advantage
• Fast re-programmability
• Standard IC fabrication Tech. is used
Disadvantage
• SRAM volatile
• Requires large area
Floating gate programming
 Tech used in EPROM and
EEPROM devices is used
 Switch is disable by applying high
voltage to gate-2 between gate-1
and drain.
 The charge is removed by UV light

Advantage:-No
Advantage:- external permanent
memory is needed to program it at
power-up
Disadvantage:-
 Extra processing steps
 Static power loss due to pull up
resistor and high on resistance
Antifuse programming methodology

 2 terminal device with an un programmed state

present very high resistance.
 By applying high voltage create a low resistance link.
Advantage:-
 Small size
 Low series resistance and low parasitic capacitance
SUMMARY
 WHY BETTER ?
 FPGA programmed using electrically programmable
switches
 Routing architectures are complex.
 Logic is implemented using multiple levels of lower
fan-in gates.
 Shorter time to market
 Ability to re-program in the field to fix bugs

FPGA DISADVANTAGE
 FPGAs are generally slower than their application-
specific integrated circuit (ASIC)
 Can't handle as complex a design, and draw more
power.
APPLICATION
 Reconfigurable computing.
 Applications of FPGAs include DSP, software-defined
radio.
 The inherent parallelism of the logic resources on the
FPGA allows for considerable compute throughput.
FPGA DESIGN AND PROGRAMMING
 To define the behavior of the FPGA the user provides a
hardware description language (HDL) or a schematic
design.
 Then, using an electronic design automation tool, a
technology-mapped net list is generated.
 The netlist can then be fitted to the actual FPGA
architecture using a process called place-and-route.
 The user will validate the map, place and route results
via timing analysis, simulation, and other verification
methodologies.
 Once the design and validation process is complete, the
binary file generated used to configure the FPGA.
THANK YOU