Design Technologies

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 Views / Abstractions / Hierarchies
Structural
Behavioral

device

Circuit

Logic
Architectural
Physical
D.Gajski, Silicon Compilation, Addison Wesley, 1988
Introduction to VLSI Design Introduction © Steven P. Levitan 1998
 N-Channel Enhancement
mode MOS FET
– Four Terminal Device - substrate bias

–The “self aligned gate” - key to CMOS

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 The MOS Transistor

Gate Oxyde
Gate
Polysilicon Field-Oxyde
Source Drain
(SiO2)
n+ n+

p+ stopper
p-substrate

Bulk Contact

CROSS-SECTION of NMOS Transistor

Digital Integrated Circuits Introduction © Prentice Hall 1995

 MOS transistors
Types and Symbols
D D

G G

S S

NMOS Enhancement NMOS Depletion

D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact

Digital Integrated Circuits Introduction © Prentice Hall 1995

 The Basic Idea…
» Voltage on the Gate controls the current
through the source/drain path
» N-Channel - N-Switches are ON when the
Gate is HIGH and OFF when the Gate is LOW
» P-Channel - P-Switches are OFF when the
Gate is HIGH and ON when the Gate is LOW
» (ON == Circuit between Source and Drain)

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 Transistors as Switches
N Switch
D
0 1
G Passes “good zeros”
S

P Switch

D
0
G 1 Passes “good ones”
S

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 ….The Rest of the Story...

» Put them in series - both must be on to

complete the circuit
» Put them in parallel - either can be on to
complete the circuit
» Generate all sorts of Switching Functions
» NOT the same as Boolean Functions.... Its
RELAY logic - pin ball machines

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 Series Parallel Structures
D
1 G
S D D
1 G G 1
D S S
1 G
S

N Channel: on=closed when gate is high

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 NMOS Transistors in Series/Parallel
Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

Digital Integrated Circuits Introduction © Prentice Hall 1995
 Series Parallel Structures(2)
D
0 G
S D D
0 G G 0
D S S
0 G
S

P Channel: on=closed when gate is low

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 PMOS Transistors in Series/Parallel
Connection

PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

Digital Integrated Circuits Introduction © Prentice Hall 1995
 Series Parallel Structures (3)

N Switch
0
S 1
G

Passes “good zeros”

D
S
D

Passes “good ones”

G

S’ 0
1
P Switch
Open Circuit, High Z
Bi-directional Switch

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 From Switches to Boolean
Functions...
 Use the Switching Functions to provide paths
to Vdd or GND
» Vdd is the source of all Truth (Vdd = = 1)
» GND is the source of all Falsehood (GND == 0)

P-channel N-channel 0
0 1
1

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 The Inverter

 True to False / False to True Converter

1/0 0/1

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 …That’s it!

 This is Non-Trivial: it defines the basis

for the logic abstraction which is
essential for all Boolean functions.
» Provide a path to VDD for 1
» Provide a path to GND for 0
» For complex functions - provide complex
paths

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 Four Views
Logic Transistor Layout Physical

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 Cross-Section of CMOS
Technology

Digital Integrated Circuits Introduction © Prentice Hall 1995

 Magic Layout of Inverter

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 Magic “Palette” of Layers

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

Modern Interconnect
 Chain of Inverters

A B C D E

Feedback loop

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 Which is which?
A B C D E

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 CMOS logic structures
– Static (logic) structures
 Complementary structures
 Pass structures
 Pseudo-NMOS structures
– Dynamic (logic) structures
 precharged
 latched
 combinations
– Memory structures
 static
 quasi-static
 dynamic
– I/O structures
Introduction to VLSI Design Introduction © Steven P. Levitan 1998
 Complementary Structures

» Big -- 2 x N transistors for N inputs

– Use the “dual” for N and P chains
– Can/should be sized for maximum
speed/minimum power-area
» Can use well known circuit minimization
techniques
– Fast
– Low static power dissipation
– Possibly high dynamic power dissipation

Introduction to VLSI Design Introduction © Steven P. Levitan 1998

 Static CMOS Circuit

At every point in time (except during the switching

transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

Digital Integrated Circuits Introduction © Prentice Hall 1995

 Static CMOS
VDD

In1
In2 PUN PMOS Only
In3

F=G

In1
In2 PDN NMOS Only
In3

VSS

PUN and PDN are Dual Networks

Digital Integrated Circuits Introduction © Prentice Hall 1995
Complementary CMOS Logic Style Construction (cont.)

Digital Integrated Circuits Introduction © Prentice Hall 1995

 Example Gate: NAND

Digital Integrated Circuits Introduction © Prentice Hall 1995

 Example Gate: NOR

Digital Integrated Circuits Introduction © Prentice Hall 1995