ITRS Spring Public Conference

Emerging Research Devices

Annecy, France
L’Imperial Palace Hotel
April 25, 2007

Jim Hutchby – SRC

DRAFT – Work in Progress – NOT FOR PUBLICATION

1 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 ITRS
Emerging Research Devices Working Group
 Hiroyugi Akinaga AIST  Phil Kuekes HP
 Tetsuya Asai Hokkaido U. Lou Lome IDA
 Yuji Awano Fujitsu  Hiroshi Mizuta Tokyo Tech
 George Bourianoff Intel/SRC  Murali Muralidhar Freescale
 Joe Brewer U. Florida  Fumiyuki Nihei NEC
 John Carruthers PSU  Wei-Xin Ni NDL
 Ralph Cavin SRC  Tak Ning IBM
 U-In Chung Samsung  Lothar Risch Infineon
 Philippe Coronel ST Me  Dave Roberts Air Products
 Erik DeBenedictis SNL  Kaushal Singh AMAT
 Simon Deleonibus LETI  Kentaro Shibahara Hiroshima U.
 Kristin De Meyer IMEC  Thomas Skotnicki ST Me
 Mike Forshaw UC London  Satoshi Sugahara Tokyo Tech
 Christian Gamrat CEA  Shin-ichi Takagi U. Tokyo
 Mike Garner Intel  Luan Tran Micron
 Shigenori Hayashi Matsushita  Ken Uchida Toshiba
 Toshiro Hiramoto U. Tokyo  Yasuo Wada Waseda U.
 Dan Herr SRC  Rainer Waser RWTH A
 Matsuo Hidaka ISTEK  Philip Wong Stanford U.
 Jim Hutchby SRC  Kojiro Yagami Sony
 Kohei Itoh Keio U.  In-Seok Yeo Samsung
 Yasuo Inoue Renesas Tech  Makoto Yoshimi SOITEC
 Seiichiro Kawamura Selete  In-K Yoo SAIT
 Hiroshi Kotaki Sharp  Peter Zeitzoff Freescale
 Nety Krishna AMAT  Yuegang Zhang Intel
 Zoran Krivokapic AMD  Victor Zhirnov SRC
DRAFT – Work in Progress – NOT FOR PUBLICATION
2 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 ITRS
Emerging Research Architectures Working
Group
 Tetsuya Asai Hokkaido U.  Phil Kuekes HP
 Ralph Cavin SRC  Lou Lome NASA/JPL
 George Bourianoff Intel  Sadas Shankar Intel
 Erik DeBenedictis SNL  Rainer Waser Aachen U.
 Michael Frank AMD  Franz Widdershoven NXP
 Dan Hammerstrom PSU  David Yeh SRC/TI
 Rick Kiehl U. Minn.  Victor Zhirnov SRC

DRAFT – Work in Progress – NOT FOR PUBLICATION

3 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 Emerging Research Devices
Organization & Component Tasks (2007)

Emerging Research Devices

Emerging
Emerging Emerging
Logic and Memory
Materials Architectures
Devices

Create a New
Chapter in 2007
DRAFT – Work in Progress – NOT FOR PUBLICATION
4 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
Evolution of Extended CMOS
Elements
Existing technologies

New technologies
Beyond CMOS
ERD-WG in Japan
year
DRAFT – Work in Progress – NOT FOR PUBLICATION
5 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 2005 ITRS ERD
Emerging Research Memory Devices
Engineered
Insulator Polymer
Nano-floating tunnel Ferroelectric Molecular
Resistance
Gate Memory barrier FET Memory Memory Memories
Change Memory
Memory
Transfer
Cell Elements 1T 1T 1T 1T1R or 1R 1T1R or 1R 1T1R or 1R
Graded 1 M-I-M
to PIDS 1 Nanocrystal insulator 2 Solid
FET with FE Electrolyte
2 Direct gate insulator M-I-M(nc)-I- Bi-stable
Device Types 3 FE tunneling
tunneling M switch
4 FE Schottky
diode
5 FE-I-FE

DRAFT – Work in Progress – NOT FOR PUBLICATION

6 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 2007 ITRS ERD
Capacitance-based Memory Technologies
Engineered
Ferroelectric
tunnel barrier
FET Memory
Memory
Charge on Remnant
floating gate polarization on a
Storage Mechanism
ferroelectric gate
dielectric
Cell Elements 1T 1T
Graded FET with FE
Device Types
insulator gate insulator

DRAFT – Work in Progress – NOT FOR PUBLICATION

7 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 2007 ITRS ERD
Resistance-based Memory Technologies
New to ERD Memory Table

Ionic Memory Electron

Nanomechanical Fuse/Antifuse Polymer Molecular
Injection
memory Memory Memory Memories
Memory
electrostatically- Ion transport in
controlled solids
Storage Multiple Multiple Not Not
bi-stable
Mechanism mechanisms mechanisms known known
mechanical
switch
Cell 1T1R or 1T1R or
1T1R or 1R 1T1R or 1R 1T1R or 1R 1T1R or 1R
Elements 1R 1R
1) Solid 1) Charge
CNT bridge Electrolyte trapping
Device CNT cantilever M -I-M e.g. 2) RedOx 2) Mott M-I-M Bi-stable
Types Si cantilever Pt/NiO/Pt reaction transition (nc)-I-M switch
Nanoparticle 3) FE Barrier
effects

DRAFT – Work in Progress – NOT FOR PUBLICATION

8 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 2005 ITRS ERD
Emerging Research Logic Devices

Device

Resonant Ferromagnetic
FET [B] 1D structures SET Molecular Spin transistor
Tunneling Devices logic
CNT FET
NW FET Crossbar latch
Moving domain
NW hetero- RTD-FET Molecular
Types Si CMOS SET wall Spin transistor
structures RTT transistor
M: QCA
Crossbar Molecular QCA
nanostructure
CNN
Conventional Conventional Cross-bar and Reconfigure
Supported Architectures Conventional CNN Conventional
and Cross-bar and CNN QCA logic and
QCA

DRAFT – Work in Progress – NOT FOR PUBLICATION

9 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
> 20 >16 - 18 Critical Evaluation For each Technology Entry (e.g. 1D Structures,
sum horizontally over the 8 Criteria
Max Sum = 24
>18 - 20 < 16
Logic Min Sum = 8

Room CMOS CMOS

Logic Device Energy Operational
Performance Temp Technological Architectural
Technologies Scalability [A] Efficiency Gain [D2] Reliability
[B] Operation Compatibility Compatibility
(Potential) [C] [E]
[F] *** [G]** [H]*
1D Structures
2.4 2.5 2.3 2.3 2.1 2.8 2.3 2.8
(CNTs & NWs)
Resonant
Tunneling 1.5 2.2 2.1 1.7 1.7 2.5 2.0 2.0
Devices
SETs 1.9 1.5 2.6 1.4 1.2 1.9 2.1 2.1
Molecular
1.6 1.8 2.2 1.5 1.6 2.3 1.7 1.8
Devices
Ferromagnetic
1.4 1.3 1.9 1.5 2.0 2.5 1.7 1.7
Devices
Spin Transistor 2.2 1.3 2.4 1.2 1.2 2.4 1.5 1.7

DRAFT – Work in Progress – NOT FOR PUBLICATION

10 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 Logic Device Conclusions

Continued analysis of alternative technology entries

likely will continue to yield the same result:
Nothing beats MOSFETs overall for performing
Boolean logic operations at comparable risk levels
Certain functions, e.g. image recognition (associative
processing), may be more efficiently done in networks
of non-linear devices rather than Boolean logic gates

DRAFT – Work in Progress – NOT FOR PUBLICATION

11 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 Supplementing CMOS
A possible ultimate evolution of on-
Basis of Existing chip architectures is Asynchronous
Assessments of Heterogeneous Multi-Core with
Logic Devices Hierarchical Processors Organization
MF(n) – application-specific processor
implementing a specific macro-function
(may need specialized devices)

MF1 MF2 MF3 MF4

MF12 MF5
General
General Purpose Processor Purpose
Processor
MF11 MF6

MF10 MF9 MF8 MF7

DRAFT – Work in Progress – NOT FOR PUBLICATION

12 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 New focus of Logic Section
Consider new logic technologies that supplement
CMOS to provide enhanced hardware capability and
can be optimally executed with alternative devices
Determine appropriate metric and compare to Si on the
specialized application
Determine if proposed application contains a standard
set of “macro-functions”
Understand the performance of the device in terms of its
non-linear characteristics
Think in terms of heterogeneous co-processors
integrated with traditional CPU
DRAFT – Work in Progress – NOT FOR PUBLICATION
13 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 Direction of 2007 chapter
Retain present table that evaluates technology entries
(TEs) against CMOS devices for Boolean logic
Include a second table (new) that evaluates TEs against
CMOS for special purpose “macro-functions” e.g.
vision processing
 Think of macro functions being implemented in special
purpose co-processors
 Revise and broaden the Architecture Section to address
possible macro functions
Consider inclusion of new TEs based on enhanced
functionalities in new operations

DRAFT – Work in Progress – NOT FOR PUBLICATION

14 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 2005 ITRS ERD
Emerging Research Logic Devices

Device

Resonant Ferromagnetic
FET [B] 1D structures SET Molecular Spin transistor
Tunneling Devices logic
CNT FET
NW FET Crossbar latch
Moving domain
NW hetero- RTD-FET Molecular
Types Si CMOS SET wall Spin transistor
structures RTT transistor
M: QCA
Crossbar Molecular QCA
nanostructure
CNN
Conventional Conventional Cross-bar and Reconfigure
Supported Architectures Conventional CNN Conventional
and Cross-bar and CNN QCA logic and
QCA

Sub-
Categorize
Molecular
and Spin

DRAFT – Work in Progress – NOT FOR PUBLICATION

15 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
Sub-categories for Spin and molecular devices
Spin
 Domain wall manipulation
 Ferromagnetic phase change (nano-domains)
 Spin transport modulation
 Spin torque transfer
 Individual and or collective spin manipulation
Molecular devices
 Crossbar coupling elements
 Molecular logic elements and interconnects
 Intra molecular logic elements

DRAFT – Work in Progress – NOT FOR PUBLICATION

16 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 Potential Supplemental Applications
 Image recognition
 Speech recognition
 DSP (cross correlation)
 Data Mining
 Optimization
 Physical simulation
 Sensory data processing (biological, physical)
 Image creation
 Cryptographic analysis
Can we define a Universal Set of Basic Macrofunctions?

DRAFT – Work in Progress – NOT FOR PUBLICATION

17 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 Proposed New Focus of Architecture Section
Consider device level architectures that optimally organize
alternative non-linear devices to supplement CMOS to
provide enhanced hardware capability

Possible Macrofunctions
 Recognition
– Examine a static data array for a specified feature
set and compare to a template
 Mining
– Finding sets of patterns in a specified pattern stream
 Synthesis
– Making predictions based on stored pattern streams

DRAFT – Work in Progress – NOT FOR PUBLICATION

18 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007
 Emerging Research Architectures
Computational Research
Architecture Implementation Network Application
Elements Activity
Homogeneous Irregular/
Symmetric cores CMOS Synthesis/GPP
Many-Core Fixed
Asymmetric Irregular/
CMOS Synthesis/GPP
cores Fixed
CMOS+Molecular Irregular/
CMOL Synthesis/GPP
Switches Fixed
Heterogeneous
Molecular Regular/
Molecular Switches Synthesis/GPP
Cross-bar Flexible
CMOS+ Irregular/
Check-point Synthesis/GPP
Ferromagnetic logic Fixed
Regular/
CNN CMOS+Sensors Recognition/Vision
Flexible
Irregular/
AMP FG-FET, SET Recognition/Vision
Morphic Fixed
Recognition
MFDT,
Bio-inspired Mixed Mining
Spin-gain transistor
Synthesis
CMOL – ‘Molecule on CMOS’ architecture GPP – General Purpose Processor
CNN – Cellular Nonlinear Network FG-MOS – Floating Gate MOS devices MFTD – multiferroic
AMP – Associative Memory Processor SET – single electron transistor tunnel diode
 Messages
 Scope: Broaden scope to encourage emerging technologies both to
supplement CMOS as well as eventually to invent the new “switch”.
 Materials Section: Spin out a new cross-cut chapter on Emerging
Research Materials.
 Memory Section: Will add NEMS mechanical memory to section.
– Divide Emerging Memory Tables into Resistive and Capacitive subcategories
– Update section in 2007.
 Logic Section: Considering reformulation of Logic Device Section
to encourage high potential, but high risk approaches while
maintaining Technology Entry evaluation function.
– Create subcategories for key Technology Entries (e.g. Spin &
Molecular logic).
– Re-considering status of candidate Technology Entries.
– Re-structuring Logic Section via Emerging Logic Workshop in
September.
 Architecture Section: Revise to focus on encouraging research to
explore optimal organization of emerging non-linear devices to
efficiently realize macro-functions to supplement the CMOS
platform technology.
DRAFT – Work in Progress – NOT FOR PUBLICATION
20 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007