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1
Overview
Topics include
• Pipelining
• Latency
• Demultiplexing
• Multiplexing
• Clock fanout and distribution
• Clock skew and fine timing adjustments
• Clock signal sources
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Logic devices and high-speed designs
Pipelining & latency
Consider the multi-bit adder, A + B
A: 0 to 31 B: 0 to 31 Cn: 0 or 1
F: 0 to 31 G : 0 or 1
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Pipelining & latency
18-bit adder Note:
Consider the propagation delay (typical) The adder is combinational
An, Bn, Cn Fn : 3 ns logic, not sequential, there is
An, Bn, Cn G : 2.5 ns no clock signal
How to find T
Identify critical path (longest delay)
5:0 A, B F 3 ns
A, B G 2.5 ns
11:6 A, B F 3 ns For this configuration, the output is
Cn F 5.5 ns stable after 8 ns 125 MHz is the
A, B G 5 ns max rate for this 18-bit adder
17:12 A, B F 3 ns
Cn F 8 ns A greater number of bits (e.g., 36-bit adder) would
A, B G 7.5 ns further increase the delay, reducing the add rate
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Pipelining & latency
Multiplexed 18-bit adder
twice as much hardware to produce results twice as fast
A clock signal
has been added to
synchronize the
registers
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Pipelining & latency
Pipelining & latency
The price to be paid for achieving this speed is
• Circuit complexity
• Data latency
Some applications can tolerated large latency
Examples include one-way data transfers
such as TV broadcast signal
Other applications cannot tolerate much latency
Examples include two-way data exchange
such as voice communications
(calls via satellite have latency of ~ 0.5 s)
Techniques to further speed up the add process
If a 6-bit add takes 3 ns
a 2-bit add should take ~ 1 ns
a 1-bit add should take ~ 0.8 ns
Theoretically could do adds as fast as 1.5 ns (667 MHz) with 18 add stages
and 36 clock cycles of latency
Note also that this approach requires a large number of clock signals (not
shown)
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High-speed digital design examples
Consider a data acquisition (DAQ) system
Analog signals are digitized and recorded
• Example applications include –
oscilloscopes, radar receiver
The maximum bandwidth of the
acquired signal is limited by the
ADC clock frequency
The precision of the digitized signal
is limited by the number of bits
in the ADC WE: write enable
The length of the data record is limited
by the memory size (2N)
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High-speed digital design examples
Consider an arbitrary waveform generator (AWG) system
Analog waveforms are produced from
stored digital records
• Example application –
radar waveform generation
The maximum bandwidth of the
output signal is limited by the
DAC clock frequency
The precision of the digitized signal
is limited by the number of bits in the DAC
The length of the waveform is limited by the memory size (2N)
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High-speed digital design examples
Data acquisition system
Consider the case where X = 8 bits, N = 16 64k word vector
1-GHz clock rate, maximum record length is 65.5 s
Key to the DAQ operation are the address generator and the memory
This design requires a 16-bit synchronous counter with preset inputs
– Not a ripple counter
The Addr_CLK must be the system clock (1 GHz)
The memory write cycle time < 1 ns
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High-speed digital design examples
The ADC’s 1:2 demux doubles the memory’s write time to 2 ns
4:1 DEMUX 12
High-speed digital design examples
High-level timing for system with 2:1 ADC demux and 4:1 demux on PCB
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High-speed digital design examples
Just as demultiplexing relaxed the DAQ timing requirements,
multiplexing eases the arbitrary waveform generator’s timing challenges
4:1 MUX
A 4:1 mux will reduce the data rate from each memory device by 4
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High-speed digital design examples
Integrating a multiplexer in the digital-to-analog converter
allows the converter to operate at higher rates
Integrated
1:2 Mux
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High-speed digital design examples
General design rules for these high-speed applications
• Keep uniform line lengths within a data bus to ensure constant signal
latency
• Jitter in the clock signal (due to clock generator circuit) will result in
phase noise in the data
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Clock signal issues
Clock signals provide a time reference for the entire system
Issues to consider regarding clock signals
Clock fanout and distribution
Clock skew and fine timing adjustments
Clock division: fCLK/2, fCLK/4, …
Clock signal generation
Clock fanout
Consider case where multiple registers must be clocked simultaneously
However the fanout limit of the
technology is ~ 5 (3 to 10)
Clock fanout buffers
Intended to provide multiple
copies of the clock signal
with equal latencies
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Clock skew
Clock skew describes when timing signals arrive at
different components at different times
Possible causes include
Clock buffer skew
Mismatched trace propagation delay
Capacitive loading or coupling
Gate-to-gate skew:
20 ps (typ), 50 ps (max)
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Clock skew
Even with low-skew clock buffers, some clock skew will remain
Timing variations can compound as devices are cascaded leading to
increaed uncertainty
Impact?
System timing variations reduced timing margin
How to compensate for clock skew?
For critical timing applications, we can employ delay adjustments
Delay line (passive) delay depends on length
Gate delay (active) delay depends on gate characteristics
Example
Consider two clock (or data) lines we wish to synchronize using delay line
variations
By changing jumper
connections can make
tB < tA or tB = tA or tB > tA
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Clock skew
Similar schemes for varying signal delay.
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Clock skew
Problem
Jumpers may cause impedance mismatch reflections
Using surface mount strips close the gaps helps reduce mismatches
Problem
Occupies significant board area
Hard to implement at chip level or in MCM
Implement jumper selection electronically
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Clock division
Subharmonics of the clock signal (fCLK/2, fCLK/4, …) can be produced using
simple flip-flops configured as clock frequency dividers
The output signals have a 50% duty cycle regardless of the input signal’s
duty cycle
Shift registers can be used to divide the signal frequency by other integer
multiples (know as ring counters or Johnson counters)
Various duty cycles can be produced from these configurations
Ring counter
Johnson counter
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Clock sources
Clock signals are used to provide a timing reference
Typically only one clock oscillator is used per system
In computers, higher frequency signals may be derived from a single
oscillator through frequency multiplication (e.g., PLL)
In radar systems, the radar frequency, the A/D sample clock, and other
timing and frequency signals are derived from a master clock oscillator
(an exception would be the clock that drives the DSP which operates
asynchronously from the rest of the system)
Specifying the clock oscillator for digital apps, consider several parameters
• Output voltage level (TTL or ECL, not sinusoidal with zero mean)
• Frequency (MHz, GHz) nominal operating freq @ nominal temp & voltage
• Stability (ppm) long-term frequency drift driven by temp, aging, voltage
• Rise/Fall time (ps)
• Waveform symmetry (%) may want to use CLK and CLK for split phase timing
• Environmental factors temperature range, shock/vibration
• Package DIP vs. SMT metal vs. plastic or ceramic
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Clock sources
Stability factors
Temperature – quartz crystals used as resonant elements
• Piezoelectric effect
Several varieties
Non-compensated – large f / T
Temperature compensated – less f / T
Oven-controlled – T is constant
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Clock sources
Various methods available to characterize clock jitter (phase noise)
Spectral analysis
An ideal clock signal has spectral energy at the fundamental and harmonic
frequencies only
Jitter (phase noise) causes a broadening of the spectral lines
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Clock sources
Converting jitter from measured phase noise
RMS
jitterRMS
o
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Clock sources
Delay line method of characterizing clock jitter
Beat a sample of the clock signal
with a delayed version of itself
v1 cos t 1
v 2 cos t 2
Mixer produces and terms
the LPF rejects the term leaving v0
v 0 cos 1 2 cos
For fixed delay value, , and a stable
v0 varies as changes
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Clock sources
Example data sheet
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Clock sources
For testing purposes, it is useful to vary the clock frequency
Finding the maximum operating clock frequency
In laboratory testing we can use a variable clock generator (if you have one)
Older versions have a maximum clock output frequency of 250 MHz
RT = Zo (50 )
C1, C2 (2 f C)-1 << RT (< 1 )
L 2f L >> RT (> 1 k)
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