Mismatch Modeling of MOS

Transistors for Deep Sub-micron

Technologies

Rasit Onur Topaloglu

rtopalog@cse.ucsd.edu
University of California at San Diego
Computer Science and Engineering Department
La Jolla, CA, 92093, USA
 Outline

-Mismatch at transistor, circuit and VLSI levels

-Modeling Challenges and Requirements in Deep Sub-Micron
-Optimizations to Avoid Mismatch
-Past and Present Mismatch Modeling Approaches:
-Electrical & Empirical Models
-Layout-based Models
-BSIM-based Models
-Physics-based Models
-Insights for Future Models for Mismatch
-Summary & Conclusions
Semiconductor Manufacturing Steps

silicon •Wafer is created

silicon dioxide •Wafer is oxidized

silicon

photoresist
silicon dioxide
silicon •Wafer is covered with photoresist

photomask
photoresist •A photomask is placed on wafer
silicon dioxide
silicon
Semiconductor Manufacturing Steps
UV radiation
photomask
photoresist •Wafer is exposed to ultra-violet
silicon dioxide
silicon (UV) radiation

photoresist
silicon dioxide •Unexposed regions dissolved
silicon

photoresist
silicon dioxide •Unprotected oxide etched
silicon

silicon dioxide •Photoresist removed.

silicon Wafer is ready for doping
 Possible Causes of Mismatch
doping
silicon dioxide
silicon •Wafer is doped

silicon dioxide
doped regions •Doping creates n or p-type wells

•Mismatch is caused by variations in the processing stages

ex. photomask misalignment, difference in doping gradients, etc.
•These variations can depend on the process (PVE), or they can be
random effects (RE)
•Mismatch negatively influences the design, which assumes accurate
matching of electrical parameters between matched transistors
 Transistor Operation and Mismatch
VDD Vth=threshold voltage
D=drain
ID quadratic
ID G=gate
D increase S=source
G
VG VDS V=voltage
VGS
S Vth I=current
L=channel length
GND W=channel width
Schematic view VGS n=channel mobility
ID
of transistor Cox=oxide capacitance
VG Increasing VGS
GND VDD
L
G
S D Drain current formula:
ID
1 W
I D   n Cox VGS  Vth 
2

Physical view VDS 2 L

Mismatch = variation in drain current of matched transistors

 Impact of Mismatch on a Circuit
Mismatch = variation in drain current of matched transistors
•Mismatch most important in analog circuits
•Analog circuits implement a linear function within a local
input space by strictly optimizing circuit parameters
M=transistor
i=input
G=gain

VOUT

Vi1 M1 M2
Vi2

A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2)

•Proper circuit operation requires precision matching of certain transistors
 Impact of Mismatch on a Circuit
Mismatch = variation in drain current of matched transistors
•Mismatch most important in analog circuits
•Analog circuits implement a linear function within a local
input space by strictly optimizing circuit parameters
W=width

VOUT

Vi1 W1=300m
W2=300m
Vi2

A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2)

•Proper circuit operation requires precision matching of certain transistors
 Impact of Mismatch on a Circuit
Mismatch = variation in drain current of matched transistors
•Mismatch most important in analog circuits
•Analog circuits implement a linear function within a local
input space by strictly optimizing circuit parameters
Vth=threshold
voltage
G=gain

VOUT

Vth1=0.7V
Vi1 Vth2=0.7V
Vi2

A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2)

•Proper circuit operation requires precision matching for certain transistors
 Impact of Mismatch on a Circuit
Mismatch = variation in drain current of matched transistors
•Mismatch most important in analog circuits
•Analog circuits implement a linear function within a local
input space by strictly optimizing circuit parameters
Id=drain current

VOUT

Id1=1mA
Vi1 Id2=1mA
Vi2

A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2)

•Proper circuit operation requires precision matching for certain transistors
 Process Variations and Mismatch
PVE=process variation effects
RE=random effects

W1 W2 G
Nominal :
VOUT 300 300 100
PVE+RE
causing mismatch:
Vi1 300 300
303 303 303 102
Vi2 297 297 98
PVE+RE not
causing mismatch:
Iref
300+2+-2 300+2+1 303 300 99
297 300 90
PVE RE PVE RE G G

•Mismatch deteriorates circuit performance, in the limit,

causes the circuit to escape optimal operating region W1when W1when
•PVE and RE’s add up; they may or may not create W2=W1 W2=300
a mismatch that effects circuit operation according to specifications
 Impact of Mismatch on VLSI Design
Mismatch causes soft errors (reduction in gain, higher output R)
-Yield loss
Critical mismatch necessitates re-design
-Increased time to market
Mismatch effects are not easily predictable
-Optimization of circuit without accurate
consideration of mismatch is barely lost time

•We need to design for mismatch

•We need to estimate effects of mismatch : both require models
 Why Mismatch Models Necessary for
Analog Design Flow?

Behavioral level design and simulations

Select architecture and technology

Manual design

SPICE simulations

Optimizations

Test & diagnosis after production

Costly redesign needed due to late observation of mismatch effects

 Why Mismatch Models Necessary for
Analog Design Flow?

Behavioral level design and simulations

Select architecture and technology

Manual design

SPICE simulations

Optimizations

Test & diagnosis after production

Costly redesign needed due to late observation of mismatch effects

Essential to help model mismatch as soon as possible so as to

accomplish heavy reduction in number of iterations
 Outline

-Mismatch at transistor, circuit and VLSI levels

-Modeling Challenges and Requirements in Deep Sub-Micron
-Optimizations to Avoid Mismatch
-Past and Present Mismatch Modeling Approaches:
-Electrical & Empirical Models
-Layout-based Models
-BSIM-based Models
-Physics-based Models
-Insights for Future Models for Mismatch
-Summary & Conclusions
Model Requirements for each Step of the Design Flow

Behavioral level design and simulations Mismatch Predictive models

Select architecture and technology

Manual design Manually applicable models

SPICE simulations Accurate models for simulation

Optimizations

Test & diagnosis after production Models for Test and diagnosis
 Worst-Case Estimations Fail in Deep Sub-Micron
Bandgap
reference actual pdf
circuit
Vb1
Vb2

Iref Vb3 99 %
falls in
Worst-case limits for this range
an output parameter OpAmp

Iref

Current mirror

•Worst-case propagation between blocks results in overestimation of errors

•Designing while considering such large variations impossible in DSM
•Correlations between parameters accentuate this error
New models should avoid worst-case estimations
 The Increasing Importance of Random Effects
Fabrication accuracy cannot keep up with feature size shrinkage rate, as:
•Errors occurring from diffusion cause PV distributions that have similar
   across different technologies

PVE

tox (x40nm) newer technology tox (x4nm)

Wafer radius Wafer radius

RE

•Mismatch groups closer than ever before, therefore:

REs assume increased importance compared to previous technology
New models should be able to consider random effects
 Outline

-Mismatch at transistor, circuit and VLSI levels

-Modeling Challenges and Requirements in Deep Sub-Micron
-Optimizations to Avoid Mismatch
-Past and Present Mismatch Modeling Approaches:
-Electrical & Empirical Models
-Layout-based Models
-BSIM-based Models
-Physics-based Models
-Insights for Future Models for Mismatch
-Summary & Conclusions
 Layout Optimizations
tox=oxide thickness

A B A B B A
tox=4.2nm tox=4.2nm
tox=4.1nm tox=4.1nm
tox=4.0nm
tox=4.0nm

Common centroid layout style

standard layout style iso-parameter contours for a physical parameter such as tox

•Statistical average of a parameter would differ a lot on matched

transistors without optimizations causing significant mismatch
•Layout optimizations try to disperse the effects of on-chip
gradients between matched transistors A and B equally
 Criticism of Layout Optimization
iso-parameter contours for a
physical parameter such as tox

A B B A
tox=4.2nm
tox=4.1nm
tox=4.0nm

Common centroid layout style

+Sufficient for minimal to moderate matching
-Suffers linear optimization limitations as transistors rectangular, yet
physical parameter distributions have curves
-Connecting gates, or avoiding from deteriorating effects of other
blocks on layout may be problematic
-Not quite suitable for matching ratios other than unity
 Circuit Optimizations PSD=power
A Digital-to-Analog Converter (DAC) spectral density
DAC=digital to
x1[n] 1-Bit y1[n] analog converter

Thermometer Encoder
DAC
1-Bit y2[n]
b DAC y[n]
x[n] .
. .  y[n]
.
1-Bit
x2b[n] DAC y2b [n]
x[n]
PSD
•The circuit implements an ideal staircase
transfer function between input and output
•Mismatch within DAC’s cause a related frequency
performance parameter, PSD, to fail specifications
I. Galton and P. Carbone, “A Rigorous Error Analysis of D/A
Conversion with Dynamic Element Matching,” IEEE TCAS-II, 1995
 Circuit Optimizations
A Low Harmonic DAC
PSD
x1[n] 1-Bit y1[n]

Thermometer Encoder
DAC
1-Bit y2[n]
DAC

Scrambler
x[n] b
.
. . .  y[n] frequency
. .
1-Bit
x2b[n] DAC y2b [n]

•Scrambler randomly selects 1-Bit DACs to be used in computation

I. Galton and P. Carbone, “A Rigorous Error Analysis of D/A

Conversion with Dynamic Element Matching,” IEEE TCAS-II, 1995
 Circuit Optimizations
A Low Harmonic DAC
PSD
x1[n] 1-Bit y1[n]

Thermometer Encoder
DAC
. 1-Bit y2[n]
. DAC

Scrambler
x[n] b
. .  y[n]
. . frequency

1-Bit
x2b[n] DAC y2b [n]

•Scrambler randomly selects 1-Bit DACs to be used in computation

•Mismatch in 1-Bit DAC blocks averaged, compensating

deteriorating effects of mismatch on distortion

I. Galton and P. Carbone, “A Rigorous Error Analysis of D/A

Conversion with Dynamic Element Matching,” IEEE TCAS-II, 1995
 Criticism of Circuit Optimizations
A Low Harmonic DAC
x1[n] 1-Bit y1[n]

Thermometer Encoder
DAC
. 1-Bit y2[n]
. DAC

Scrambler
x[n] b
. .  y[n]
. .
1-Bit
x2b[n] DAC y2b [n]

+May be the best way to optimize for a single parameter

-Architecture specific, hence requires design time
-It is usually necessary to optimize a circuit for more than one
parameter
 Outline

-Mismatch at transistor, circuit and VLSI levels

-Modeling Challenges and Requirements in Deep Sub-Micron
-Optimizations to Avoid Mismatch
-Past and Present Mismatch Modeling Approaches:
-Electrical & Empirical Models
-Layout-based Models
-BSIM-based Models
-Physics-based Models
-Insights for Future Models for Mismatch
-Summary & Conclusions
 Electrical / Empirical Parameter-based Mismatch
Modeling
•Classical ad-hoc approach by designers
•Threshold voltage mismatch is the most common model
•Worst-case conditions algebraically calculated for parameters
Ex:Mismatch modeled at input as common-mode offset voltage for a
differential pair Derivation of Vos starts with
Vos=offset voltage R1 R2 equating drain voltages:
R=resistance

+
ID1 ID2

+
I D1R1  I D2 R2
VGS1 VGS2 Drain current formula:
Vos - -
1 W
I D   nCox VGS  Vth 
2

Iref
2 L
Differential stage

B. Razavi, “Analog CMOS Integrated Circuits,” McGraw-Hill, 2000

 Derivation of Optimization Equations

Derive Vos to compensate for mismatch: Vos  VGS1  VGS 2

1 2I D  RD W / L 
Vos      Vth
2  W   RD
 nCox  
W / L 
L
R1 R2
•Terms with  come from first
ID1 ID2
order Taylor series expansion
+ +
VGS1 VGS2
•Assumption: Independence
Vos - -
between parameters
•By adding Vos, mismatch caused
CMRR=common Iref degeneration of some parameters
mode reject ratio
like CMRR avoided
Consideration of Correlations Between Parameters

•First order Taylor series taken around nominal bias point

I  f (Vth ,VGS ,..)

Method of Moments formula is applied this formula:
n
f n n
f f
 2 ( f ( P1 ,.., Pn ))   ( ) 2  2 ( Pi )    2 ij ( )( ) ( Pi ) ( Pj )
i 1 Pi i 1 j i 1 Pi Pj
Pi=parameters to be matched

•Effect of each parameter on the variance of a function of these

parameters is individually added by first term in the sum
•Correlations are considered through second term in the sum
C. J. Abel, C. Michael, M. Ismail, C.S. Teng and R. Lahri,
“Characterization of Transistor Mismatch for Statistical CAD of
Submicron CMOS Analog Circuits,” ISCAS, 1993
 Critical Analysis of Electrical-Empirical
Parameter-based Mismatch Modeling

+Suitable for back-of-the-envelope calculations

+Used when starting a design

-Usually used to acquire a worst-case estimation

-Real results are seldom worst-case, but occur according to a non-

uniform probability distribution
-No layout consideration
 Outline

-Mismatch at transistor, circuit and VLSI levels

-Modeling Challenges and Requirements in Deep Sub-Micron
-Optimizations to Avoid Mismatch
-Past and Present Mismatch Modeling Approaches:
-Electrical & Empirical Models
-Layout-based Models
-BSIM-based Models
-Physics-based Models
-Insights for Future Models for Mismatch
-Summary & Conclusions
 Layout Dependent Mismatch Modeling
2 Ap=fitting constant for area
A
 (P) 
2 p

WL
•Variance of deviation in a parameter is inversely
proportional to the area of the transistors to be matched

K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland,

“Characterization and Modeling of Mismatch in MOS
Transistors for Precision Analog Design,” JSSC, 1986
 Layout Dependent Mismatch Modeling
Ap=fitting constant for area, WL
Ap2
 2 (P)   S p2 D 2 Sp=fitting constant for distance D
between matched transistors
WL
•Variance of deviation in a parameter is inversely
proportional to the area of the transistors to be matched

•Variance of deviation in a parameter is directly proportional

to the squared distance between the transistors to be matched
•A consequent design strategy is laying out matched pairs closer
and selecting their areas as large as possible
K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland,
“Characterization and Modeling of Mismatch in MOS
Transistors for Precision Analog Design,” JSSC, 1986
J. M. Pelgrom, C. J. Duinmaijer and P. G. Welbers, “Matching
Properties of MOS Transistors,” JSSC, 1989
Extending Distance Parameter in the Fitting Model
•Distance parameter in Pelgrom’s model extended to a polynomial
model by including first order terms => higher accuracy

 2 (P)  f ( x, y)  P x,y is location on wafer

a,b,c,d fitting constants

•Change in parameter P is modeled as a function of systematic

and local variations

f ( x, y)  a( x  y )  bx  cy  d
2 2

•Function f is obtained by fitting regression curves on factory

provided manufacturing data

G. Tulunay, G. Dundar and A. Ataman “A New Approach to

Modeling Statistical Variations in MOS Transistors,” ISCAS, 2002
 Improved Stochastic Estimation
•Extensions to include inter-digitated and cross-coupled
geometries through usage of stochastic theory
y

M1 M2 M1 and M2 are matched

transistors in common-
centroid layout style

x
•Parameters (x,y) formulated using integration over pairs’ areas
•A covariance matrix for (x,y) is formulated using Gaussians as
an autocorrelation function
•Levenberg-Marquardt least squared method used to fit
parameters in the formulations to on-chip measurement data
M. Conti, P. Crippa, S. Orcioni and C. Turchetti, “Layout-
Based Statistical Modeling for the Prediction of the Matching
Properties of MOS Transistors,” IEEE TCAS-I, 2002
 Incorporation of Effective Lengths
•Suggestion of usage of effective width and lengths instead, as
dotted effective area important for matching
M1 M2 equal initial areas
for MOS channels
transistor channels (solid lines)
•Equal nominal mask areas for differing transistor shapes may
result in mismatch when lengths in real chip are considered
•If L is nominal, L-L is the effective length caused by penetration
of doping under channel region L

Leffective
•Algebraic estimation of L is possible using SPICE models
•Pelgrom’s equation used with effective lengths of transistors

S. J. Lovett, M. Welten and B. Mason “Optimizing MOS Transistor

Mismatch,” JSSC, 1998
 Higher Regression Order for Area Term

•Higher order regression using Cnm terms as fitting constants

N ,M
Cnm
 (P)  
2
Cnm : fitting constants
n,m (Wn  W ) n
( Lm  L ) m

•Builds on previous work and uses effective lengths in

denominator

•The choice of maximum regression order is questionable

T. Serrano-Gotarredona and B. Linares-Barranco, “Systematic Width

and Length Dependent CMOS Transistor Mismatch Characterization
and Simulation,” Analog IC and Signal Processing, 1999
Criticism of Layout Dependent Mismatch Modeling

All models based on improving Pelgrom’s Equation:

Ap2
 2 (P)   S p2 Dx2
WL

+Practical for an initial estimate

-Pelgrom’s model loses accuracy for longer distances

-More accurate ones requires a costly extraction procedure of
fitting constants from the process
 Outline

-Mismatch at transistor, circuit and VLSI levels

-Modeling Challenges and Requirements in Deep Sub-Micron
-Optimizations to Avoid Mismatch
-Past and Present Mismatch Modeling Approaches:
-Electrical & Empirical Models
-Layout-based Models
-BSIM-based Models
-Physics-based Models
-Insights for Future Models for Mismatch
-Summary & Conclusions
 Statistical Mismatch Modeling
•Model for space dependent mismatch:
ij : standard deviation between Pi and Pj
M
PM   AMI RI Pi : a parameter of i’th transistor
Ri : independent N(0,1) random numbers
I 2
-space for parameter P : AMI : coefficients of the random numbers
R3 •Distances represent variances in
A33 P3 -space analysis :

|13|  MN  sP DMN
|23|
|12| P2 DMN : distance between transistors
P1 A32 R2
A22 sp : fitting constant
•Once P1 is fixed to origin, location of other transistors are found
using geometry, then Aij values can be extracted on the axes
•-space analysis relates variances in parameters to distances
between transistors thus preserving space correlations
C. Michael and M. Ismail, “Statistical Modeling of Device
Mismatch for Analog MOS Integrated Circuits,” JSSC, 1992
 Principal Component Analysis (PCA) for
Preserving Correlations
P  p •Normalize each parameter
P`
p P,Q : parameters
P` : normalized parameter

1 n
ρPQ  i 1 P`Qi ` •Find correlations
n
•Apply PCA by finding
1/ 2 1
C U P` eigenvalues and eigenvectors
of C first
P` U C 1/ 2 C : principal component vector
 : diagonal eigenvalue matrix
U : eigenvector matrix
P` : normalized parameter matrix
•PCA helps preserve parameter correlations by writing each
parameter as a function of independent principal components
C. Michael and M. Ismail, “Statistical Modeling of Device
Mismatch for Analog MOS Integrated Circuits,” JSSC, 1992
 An Example of PCA Application
•PCA helps formulate normalized parameters in terms of
independent principal components:
P` U C 1/ 2

VFB` 0.69C1  0.41C2  0.46C3  0.09C4  0.26C5  0.19C6

MUZ ` 0.05C1  0.77C2  0.09C3  0.33C4  0.49C5  0.12C6
VFB` : normalized flat-band voltage
MUZ` : normalized zero bulk bias mobility
Ci : principal components, chosen unit normal

•Area relationship is obtained through using a fitting constant

•P` values are unit normal, they are used in -space analysis as
random numbers so that parameters correlations are preserved
•Remember that -space preserved distance based correlations
C. Michael and M. Ismail, “Statistical Modeling of Device
Mismatch for Analog MOS Integrated Circuits,” JSSC, 1992
 An Approach for SPICE Implementation
•SPICE parameters are perturbed directly:

delvt   Vth x1

delu 0    /  (r Vth x1  1  r2Vth x2 )

x1, x2 : unit normal random numbers
r : correlation constant
delvt=deviation in threshold voltage
delu0=deviation in mobility

•Unit normal random numbers, x1 and x2, generated

•SPICE parameters, delvt and delu0, are perturbed using
different x1 and x2 each time to simulate a new process
Q. Zhang, J. J. Liou, J. R. McMacken, J. Thomson and P. Layman,
“SPICE Modeling and Quick Estimation of MOSFET Mismatch
Based on BSIM3 Model and Parametric Tests,” JSSC, 2001
Criticism of BSIM-based Mismatch Modeling

+Considers layout
+Considers correlations
-Correlation constants are somewhat inaccurate themselves
-Requires fitting and process related constants
-Does not provide an intuitive understanding of mismatch
-Parameter inaccuracies due to extraction from wafer may be
magnified through PCA
 Outline

-Mismatch at transistor, circuit and VLSI levels

-Modeling Challenges and Requirements in Deep Sub-Micron
-Optimizations to Avoid Mismatch
-Past and Present Mismatch Modeling Approaches:
-Electrical & Empirical Models
-Layout-based Models
-BSIM-based Models
-Physics-based Models
-Insights for Future Models for Mismatch
-Summary & Conclusions
 Physics-based Mismatch Modeling

•Basic idea : Mismatch is a physical phenomenon and physical

parameters are independent
2 • Variance in electrical parameters
 e  2
  
2
  pi
written in terms of geometry dependent

i  pi 
e variances of physical parameters
e : electrical parameter
p : physical parameter
•pi’s are dependant on size and distance of transistors
•pi’s can be Vfb, Tox, W, L, 0, Nsub, etc.
•If enumeration factors are such that |e| > |i|, estimation of physical
parameter variances from electrical measurements is also possible
•Due to complex formulas, CAD tools required
P. G. Drennan and C. C. McAndrew, “Understanding
MOSFET Mismatch for Analog Design,” JSSC, 2003
 An Tractable Physics-based Mismatch Model
•Random effects mimicked through assigning pdf’s to Level0 parameters
Independent
W L NSUB VFB n tox Level0 Normal

Correlated?
Vth Cox Level1 pdf?

Correlated?
k Each node is a parameter Level2 pdf?

Graph structured using SPICE

Correlated?
ID formula hierarchy Level3 pdf?

Correlated?
gm
Level4 pdf?
R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep
Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004
 Connectivity Based Traversal
•Proposed approach provides a manually tractable estimation
•Chain rule used to relate a high level parameter to physical ones
L0 : level 0 x y
L0 NSUB Sy 
x

y x

VT0=f1(NSUB) PHI
L1

L2 VT0 VT0=f2(PHI,NSUB)

Vth=f3(PHI,VT0)
Vth L3

Vth Vth PHI + Vth VT0 + VT0 PHI

S NSUB
= S PHI
* SNSUB
S VT0
* (SNSUB
S
PHI
* SNSUB
)
R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep
Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004
 Connectivity Based Traversal
•Proposed approach provides a manually tractable solution
•Chain rule used to relate a high level parameter to physical ones

L0 NSUB

VT0=f1(NSUB) PHI
L1

L2 VT0 VT0=f2(PHI,NSUB)

Vth=f3(PHI,VT0)
Vth L3

Vth Vth PHI + Vth VT0 + VT0 PHI

S NSUB
= S PHI
* SNSUB
S VT0
* (SNSUB
S
PHI
* SNSUB
)
R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep
Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004
 Connectivity Based Traversal
•Proposed approach provides a manually tractable solution
•Chain rule used to relate a high level parameter to physical ones

L0 NSUB

VT0=f1(NSUB) PHI
L1

L2 VT0 VT0=f2(PHI,NSUB)

Vth=f3(PHI,VT0)
Vth L3

Vth Vth PHI + Vth VT0 + VT0 PHI

S NSUB
= S PHI
* SNSUB
S VT0
* (SNSUB
S
PHI
* S
NSUB
)
R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep
Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004
 Bridging Physical Aspects to Circuit Parameters
NSS T PHI NSUB TOX W L L0
egap COX L1
PHIms GAMMA L2
VFB L3

SPICE parameters VT0 L4

Vth L5
Id L6
design parameters gm L7
circuit parameters rout CMRR L8
 Critical Analysis of Physics-based Mismatch
Modeling

+Provides an intuitive understanding for mismatch

+Obviates the need for the use of correlations

+Suitable for diagnosis

-Are all physical reasons accounted for?

-May physical reasons be correlated to chemical or even

quantum-based reasons?
 Outline

-Mismatch at transistor, circuit and VLSI levels

-Modeling Challenges and Requirements in Deep Sub-Micron
-Optimizations to Avoid Mismatch
-Past and Present Mismatch Modeling Approaches:
-Electrical & Empirical Models
-Layout-based Models
-BSIM-based Models
-Physics-based Models
-Insights for Future Models for Mismatch
-Summary & Conclusions
 Insights for Future Models M5 M1
•Higher level circuit parameters for large variations
indicate highly non-linear relationships; as opposed to
M3 M4
linear ones observed for lower level parameters
•Signifies that a Gaussian assumption is not accurate
since linear sums of Gaussians are Gaussians, which
can be completely described by (,)
M2
CLK
Techniques for estimation of non-Gaussian
distributions necessary Sense Amplifier
Gain vs NCH Gain vs TOX Gain vs W

Dependence of gain to variations in M4 when M3 nominal @800MHz

 A simulation-based Proof by Contradiction
pdf of gain

Iref

~Gaussian

G1

Differential stage biased with current mirror

•Matched transistor group G1 introduced random mismatch to predict
probability distribution function (pdf) of circuit gain
 A simulation-based Proof by Contradiction
pdf of gain

G3

G2
Iref

non-Gaussian

Differential stage biased with current mirror

•Matched transistor groups G2 and G3 introduced random mismatch to

predict probability distribution function (pdf) of circuit gain
 A simulation-based Proof by Contradiction
pdf of gain

G3

G2
Iref

non-Gaussian

G1

Differential stage biased with current mirror

•High level circuit parameters may not exhibit a Gaussian-like pdf when physical
input parameters are assigned independent Gaussian distributions.

Closer-to-real probability distribution should be estimated through models

 Summary:

•Circuit optimizations : remedy for a single circuit parameter

•Layout optimizations : used whenever possible yet insufficient

•Electrical / Empirical models : used when starting a design

•Layout-based models : Pelgrom’s Equation used to incorporate
layout information
•BSIM-based models : used for direct SPICE implementation
•Physics-based models : used for better intuition and accuracy
 Conclusions

•A spectrum of mismatch models has been presented

•Deep sub-micron modeling needs has been identified as

avoiding worst-case limits, consideration of random effects and
an early estimation of mismatch

•Future models should target to obtain closer-to-real probability

distribution functions of performance parameters