COMPLEXITY MINIMISATION

IN PARALLEL PREFIX ADDER

Department
of
Electronics and Communication Engineering

Guided by: Presented by

Ms.M.Bharathi,M.Tech., Batch no.1923

Assistant Professor ECE-B

 CONTENTS

1. AIM OF THE PROJECT

2. INTRODUCTION
3. LITERATURE REVIEW
4. PROBLEM IDENTIFICATION WITH DESCRIPTION
5. PROPOSED METHODS FOR PROBLEM SOLUTION
6.DETAILED DESCRIPTION OF PROPOSED METHOD
7.RESULTS WITH JUSTIFICATION
8.TOOLS USED
9.CONCLUSION
10.REFERENCES
 AIM OF THE PROJECT

• Currently, parallel prefix adders (PPA) are considered effective combinational circuits for performing the binary

addition of two multi-bit numbers. These adders are widely used in arithmetic-logic units, which are parts of modern

processors, such as microprocessors, digital signal processors, etc. This paper deals with kogge-stone adder, which is

one of the fastest PPA. When performing the schematic implementation, this adder has a large hardware complexity.

Therefore, in this work for reducing its hardware complexity the scheme of Modified ppa has been developed. The

performance parameters considered for the comparative analysis of the presented adders are: the number of logic

gates, quine-complexity and maximum delay obtained by using Xilinx ISE design suite for simulation and hardware

Implementation using spartan-6 FPGA. As a result, when simulation of 32-bit adder, kogge- stone adder and modified

PPA have similar maximum delay. However modified PPA has reduced hardware complexity compared to kogge-

stone adder.
 INTRODUCTION
 Parallel prefix adders (PPA) are considered effective combinational circuits for performing
the binary addition of two multi-bit numbers. These adders are widely used in arithmetic-
logic units, which are parts of modern processors, such as microprocessors, digital signal
processors, etc.
 The need for a parallel prefix adder (ppa) is that it is primarily fast when
compared with a ripple carry adder.
 PPA circuits use a tree network to reduce the latency to O(log2n). n where ‘n’ represents the
number of bits
 Kogge-stone adder, which is one of the fastest PPA. When performing the schematic
implementation, this adder has a large hardware complexity. Therefore, the work for
reducing its hardware complexity the scheme of modified PPA has been developed.
 The performance parameters considered for the comparative analysis of the presented adders
are: the number of logic gates, quine-complexity and maximum delay .
 As a result, when simulation of 32-bit adder, kogge-stone adder and modified PPA have
similar maximum delay. However modified PPA has reduced hardware complexity compared
to kogge-stone adder.
 The proposed architectures have the least number of computation nodes when compared with
existing one’s. This reduction in hardware of the proposed architectures helps to reap a
benefit in the form of reduced power and power-delay product.
 LITERATURE SURVEY
MOTIVATION:
 In processors and in digital circuit designs, adder is an important component. As a result, adder is
the main area of research in VLSI system design for improving the performance of a digital
system.
 The performance depends on power consumption and delay.
 In vlsi technology, parallel prefix adders are known to be efficient. Adders are not only used for
arithmetic operations, but also for calculating addresses and indices.
S.No. Paper Title Author Published year

1. Delay Analysis of Parallel-Prefix Adders Geeta Rani June, 2014

2. Design and implementation of faster parallel Sunil.M, Ankith.R.D January, 2014

prefix Kogge Stone adder. Manjunatha.G.D and
Premananda.B.S.

3. Design of Kogge-Stone for fast addition. Athira.T.S, Divya.R, Karthik.M, February, 2017
Manikandan.A.

4. Design and Implementation of High Performance CH. Sudha, Rani, CH. September, 2014
Parallel Prefix Adders. Ramesh
1. Geeta Rani, Sachin Kumar. “Delay Analysis of Parallel-Prefix Adders”.
International Journal of Science and Research (IJSR), ISSN: 2319-7064, Impact
Factor (2012): 3.358. Volume 3 Issue 6, June, 2014. pp. 2339.

This paper is a survey on the various Parallel-Prefix adders. This survey shows the various
aspects of the parallel-prefix adder and there specifications. Kogge-Stone, Han-Carlson
adders require a large number of parallel wiring for wide bit adders. Sklansky architecture
becomes slow due to its high fan-out. When interconnect is considered Han-Carlson become
attractive one as it requires only half the number of columns. Individually specifications are
like Kogge-Stone has least logic levels but hard to P and G. Ladner-Fischer has a bit more
logic levels and high fan-out. Han-Carlson has more logic levels but less cells. Sklansky has
least logic levels and highest fan-out. If wire capacitance is neglected Kogge-Stone adder is
the best among the others.
2. Sunil.M, Ankith.R.D, Manjunatha.G.D and Premananda.B.S. Design and implementation of faster
parallel prefix Kogge Stone adder. International Journal of Electrical and Electronic Engeering & Tele
communications 2014. ISSN 2319 – 2518. Vol. 3, No. 1, January 2014. pp. 116

In tree adders, carries are generated in parallel and fast computation is obtained at the expense of increased area
and power. The main advantage of the design is that the carry tree reduces the number of logic levels (N) by
essentially generating the carries in parallel. The parallel-prefix tree adders are more favorable in terms of speed
due to the complexity 𝑂(𝑙𝑜𝑔2 𝑁) delay through the carry path compared to that of other adders.

Grey cells are required for computation of generate bit in final stage and thus cannot be removed. Black cells are
the only redundant cells in tree adders. The removal of redundant cells can be performed in different ways, but not
all changes give the desired results. Thus all changes which are going to be done have to be done in perspective of
speed. Analyzing from the last stage gives us a much better understanding of the redundant cells. In the last stage
there are no redundant cells as it contains only grey cells and hence none of them can be removed.
3. Athira.T.S, Divya.R, Karthik.M, Manikandan.A. Design of Kogge-Stone for fast addition. Proceedings
of 34th IRF International Conference, 26th February 2017, Bengaluru, India. ISBN: 978-93-86291-639.
pp. 27-28.

Adders use the combinations of logic gates to combine binary values for obtaining the sum. The adders are
sub divided according to their ability to accept and combine the digits. Parallel-Prefix adders perform
parallel addition i.e. more important in microprocessors, DSPs, mobile devices and in other high speed
applications. The reduction of logic complexity and delay by the Parallel Prefix Adders enhance the
performance with factors like delay and power. Therefore the Parallel- Prefix adders are the suitable element
in the high speed arithmetic circuits. The major problem for binary addition using RCA is the carry chain.
Increasing the input operand width, increases the carry chain length. The worst case occurs when the carry
travels the lengthened possible path starting from the Least Significant Bit (LSB) to the Most Significant Bit
(MSB). In order to reduce the delay in RCA (or) to propagate the carry in advance, we considering for carry
look ahead adder. Basically this type of adder works on two operations called propagates and generate.
Increasing the adder bit width, increases the carry complexity. So higher bit CLA designing becomes
complexity. In order to compute the carry in prior without delay and complexity, there is a idea called
Parallel prefix approach
TYPES OF PARALLEL PREFIX ADDERS:

1)BRENT-KUNG

2)KOGGE STONE

3)HAN-CARLSON

4)SKLANSKY

5)LADNER-FISCHER
IMPLEMENTATION OF PARALLEL PREFIX ADDER
 PROBLEM IDENTIFICATION WITH DESCRIPTION
There are 3 steps in prefix addition method.
1.Pre-processing: Involves creation of generate and propagate signals.
Generation(g)=A.B
Propagation(p)=A^B
2.Prefix computation: PPA construction depend on notion of group carry propagate and group
generate signals.
G=Gi +Pi .Gi-1 P=Pi. Pi-1
3.Post-processing:involves formation of carry and sum bits for each individual operand bit.
CI=G[I:0] SI=PI^CI-1
 Existing Method
For fast arithemetic computation,we have kogge stone adder
Kogge Stone Adder is a parallel prefix form carry look ahead adder. It generates
carry in O (logn) time and is widely considered as the fastest adder and is widely
used in the industry for high performance arithmetic circuits. In Kogge Stone
Adder, carries are computed fast by computing them in parallel at the cost of
increased area.
KOGGE STONE ADDER

Level-1

Level-2

Level-3

Level-4
• This adder computes gi and pi signals for the pre-processing stage. Then at the first level
(l=1) of prefix tree, gi:k and pi:k signals of 2-bit are computed within the same time. At the
second level (l=2) of prefix tree, gi:k and pi:k of 4-bit are calculated by using the result of 2-
bit at level 1. Therefore, the actual carry-out value of the 4th bit would be available while the
calculations at level 2 are being computed. At the third level (l=3) of prefix tree, the carry-out
of the 8th bit is computed by using the 4th bit carry result. The same method adopted at level
3 is applied to get carry-out values of the 16th bit in fourth level (l=4) and etc. All other
carries of bit are also computed in parallel. Finally, at the final processing stage the sums are
computed from these final carry-out signals of the prefix tree
• In black cell,we will find propagation and generation.
• In gray cell,we will find generation only.
 DISADVANTAGES OF KOGGE STONE ADDER

 More number of logic gates

 Quine complexity
 PROPOSED METHODS FOR PROBLEM SOLUTION
MODIFIED PPA
The estimation of hardware costs of kogge-stone adder has a great number of logic gates and
quine-complexity used in the schematic implementation.
Therefore, in the present work for reducing its hardware complexity a modified parallel prefix
adder is developed. Then, the comparison of the two presented adders is made by the following
parameters: the number of logic gates, quine complexity, as well as the delay .
 MODIFIED PARALLEL PREFIX ADDER

Quine complexity QK.S and the number of

logic gates Ck.s in the kogge-stone adder
are given by
Ck.s=3n(log2n)-n+4
QK.S=6n(log2n)-2n+8

The number of logic gates are given by

Cmodified PPA=[3n/2(log2n+1)]+2n-2
Qmodified PPA=3n(log2n+1)+4n-4
 COMPARISION BETWEEN KOGGE STONE AND MODIFIED
PARALLEL PREFIX ADDER

KOGGE-STONE ADDER MODIFIED PPA ADDER

Type of No. of No. of No. of Quine Type of No. of No. of No. of Quine
PPA levels schemat logic comple PPA levels schemati logic comple
in ic nodes gates xity in c nodes gates xity
prefix in prefix prefix in prefix
tree tree tree tree
8-bit 3 17 68 136 8-bit 3 15 62 124
16-bit 4 49 180 360 16-bit 4 39 150 300
32-bit 5 129 452 904 32-bit 5 95 350 700
 APPLICATION :
• DADDA MULTIPLIER:
The Dadda multiplier is a hardware multiplier design invented by computer scientist Luigi
Dadda in 1965. It is similar to the Wallace multiplier, but it is slightly faster (for all operand sizes)
and requires fewer gates (for all but the smallest operand sizes).
In fact, Dadda and Wallace multipliers have the same three steps for two bit strings and of
lengths and respectively:
1.Multiply (logical AND) each bit of w1, by each bit of w2 , yielding l1.l2 results.
2.Reduce the number of partial products by stages of full and half adders until we are left with at
most two bits of each weight.
3.Add the final result with a conventional adder
WALLACE MULTIPLIER DADDA MULTIPLIER
 ALGORITHM
A(8-BIT) B(8-BIT)
Step-1

Step-2

Step-3

Step-4

Step-5
 RESULTS
KOGGE STONE ADDER(16-BIT):
RTL Schematic –Block diagram
 Behavioral Model simulation result

INPUTS&OUTPUTS

A=13652
B=10812
CIN=1
SUM=24465
KOGGE STONE ADDER(32-BIT):

RTL Schematic –Block diagram

 Behavioral Model simulation result
INPUTS&OUTPUTS

A=00101010100000011111111111110000

B=00010001000000000011111111111111

CIN=1

SUM=00111011100000100011111111110000

COUT=0
 Behavioral Model simulation result

INPUTS&OUTPUTS

A=3329293824

B=453112035

CIN=1

SUM=3782405860

COUT=0

A=715402032

B=715402256

CIN=1

SUM=1430804289

COUT=0
MODIFIED KOGGE STONE ADDER(16-BITS):
RTL Schematic-Block diagram
 Behavioral Model simulation result

INPUTS & OUTPUTS:

A=0011010101010100

B=0010101000111100

SUM:0010111110010010000

A=0011001010101000

B=0001001010100000

SUM=00100010101001000
 Behavioral Model simulation result

INPUTS&OUTPUTS:

A=12968
B=4768
SUM=17736

A=13652
B=10812
SUM=24464
MODIFIED KOGGE STONE ADDER(32-BIT):
RTL Schematic-Block Diagram
 Behavioral Model simulation result

INPUT&OUTPUT

A= 00101010101010101010000001111110
B= 10011110000111000111000111001100
SUM=011001000110001110001001001001010
 Behavioral Model simulation result

INPUTS&OUTPUTS

A= 2863236912
B= 615075843
SUM=3478312755

A= 715825278
B= 2652664268
SUM=3368483546
DADDA MULTIPLIER:

RTL Schematic-Block diagram

 Behavioral Model simulation result

INPUTS&OUTPUTS

A=10101001
B=01010011

PRODUCT=0011011011001011
 Behavioral Model simulation result

INPUTS&OUTPUTS

A=169
B=83
PRODUCT=14027
 NO. OF GATES :
MODIFIED KOGGE STONE
KOGGE STONE ADDER(16-BIT) : ADDER(16-BIT):
Number of slices=50 Number of slices=30
DELAY:

KOGGE STONE ADDER MODIFIED KOGGE STONE ADDER

Delay=12.843ns Delay=12.843ns
NO. OF GATES :
MODIFIED KOGGE STONE
KOGGE STONE ADDER(32-BIT) : ADDER(32-BIT):
Number of slices=136 Number of slices=82
DELAY:
MODIFIED KOGGE STONE
KOGGE STONE ADDER(32-BIT) ADDER(32-BIT)
Delay=14.72ns Delay=20.47ns
 TOOLS USED

TOOL- Xilinx ISE Design Suite 14.5

CODE: Verilog
 CONCLUSION

 In this, we have implemented the standard 16bit and 32 bit Kogge-stone adders
 And modified parallel predix adders.
 We have designed a dadda multiplier using parallel prefix adder.

 Then, a comperative analysis of parameters and simulation results of the presented

adders have been carried out.

 As a result, we have shown that the modified parallel prefix adder proposed in the
work has an advantage in terms of hardware complexity in comparison with the
known structure of kogge-stone adder.
 REFERENCES
[1] Geeta Rani, Sachin Kumar. “Delay Analysis of Parallel-Prefix Adders”. International Journal of Science and
Research (IJSR), ISSN: 2319-7064, Impact Factor (2012): 3.358. Volume 3 Issue 6, June, 2014. pp. 2339.

[2] Reto Zimmermann. Binary Adder Architectures for Cell-Based VLSI and their Synthesis. Thesis for the degree of
Doctor of technical sciences. Zurich. 1997. pp. 5-7.

[3] Sunil.M, Ankith.R.D, Manjunatha.G.D and Premananda.B.S. Design and implementation of faster parallel prefix
Kogge Stone adder. International Journal of Electrical and Electronic Engineering & Telecommunications 2014. ISSN
2319 – 2518. Vol. 3, No. 1, January 2014. pp. 116.

[4] Athira.T.S, Divya.R, Karthik.M, Manikandan.A. Design of Kogge-Stone for fast addition. Proceedings of 34th IRF
International Conference, 26th February 2017, Bengaluru, India. ISBN: 978-93-86291-639. pp. 27-28.

[5] CH. Sudha, Rani, CH. Ramesh. Design and Implementation of High Performance Parallel Prefix Adders.
International Journal of Innovative Research in Computer and Communication Engineering. An ISO 3297: 2007
Certified Organization. Vol.2, Issue 9, September 2014. pp. 5900.
THANK YOU!