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1
Dr.Raja
EE141Paul Perinbam Introduction
Very-large-scale integration (VLSI)
2
Dr.Raja
EE141Paul Perinbam Introduction
WHY VLSI?
Integration improves the design:
lower parasitics = higher speed;
lower power;
physically smaller.
Integration reduces manufacturing cost-
(almost) no manual assembly.
3
Dr.Raja
EE141Paul Perinbam Introduction
WHY BUILD INTEGRATED
CIRCUIT?
IC Technology driving the whole innovative devices
and systems which effected the way we live.
ICs are much smaller.
consume less power than discrete component.
– easier to design and manufacture.
– more reliable than discrete system.
– can design more complex system.
The growth of electronic industry.
Dr.Raja
EE141Paul Perinbam Introduction
THE ADVANTAGES OF ICs OVER THE DISCRETE
COMPONENTS
• Size
much smaller both transistor and wires.
leads to smaller parasitic resistances, capacitances
and inductances
• Speed
– communication within the chips are much faster than
between a chips on PCB.
– High speed of circuits on-chip due to smaller size.
• Power Consumption
– Logic operation within the chip consumes much less
power.
– smaller size -> smaller parasitic capacitances and
resistance -> require less power to drive the circuit.
Dr.Raja
EE141Paul Perinbam Introduction
ADVANTAGES OF IC AT SYSTEM
LEVEL
• Smaller Physical Size
– can make a small electronic appliances. ie.
Portable TV, handheld cellular telephone…
Dr.Raja
EE141Paul Perinbam Introduction
VLSI AND YOU
Microprocessors:
personal computers;
microcontrollers.
DRAM/SRAM.
Special-purpose processors.
Dr.Raja
EE141Paul Perinbam Introduction
VLSI chips are used in:
Computers
Cellular phones
Gaming systems
DVD players, TVs
Watches
Cars
Medical devices
Pacemakers and coffee pots
Space stations
Greeting cards
…
8
Dr.Raja
EE141Paul Perinbam Introduction
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470
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Dr.Raja
EE141Paul Perinbam Introduction
ENIAC - The first electronic computer (1946)
10
Dr.Raja
EE141Paul Perinbam Introduction
The Transistor Revolution
First transistor
Bell Labs, 1948
11
Dr.Raja
EE141Paul Perinbam Introduction
First Working Integrated Circuit
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Dr.Raja
EE141Paul Perinbam Introduction
The First Integrated Circuits
Bipolar logic
1960’s
13
Dr.Raja
EE141Paul Perinbam Introduction
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
14
Dr.Raja
EE141Paul Perinbam Introduction
Intel Pentium (i7) Processor
4.7 Billion
Transistors
540 mm2 Area
8-Core
2.6 GHz
15
Dr.Raja
EE141Paul Perinbam Introduction
I
E M N
N A
I S V
G R
D A C E
I K
E N A S
N E
A D D T
E T M
E I E
R N N
S G T
S
Super Chip
16
Dr.Raja
EE141Paul Perinbam Introduction
System Specifications
Circuit Design
Physical Design
Manufacturing
Bottom
Design Level
Finished VLSI Chip
17
Dr.Raja
EE141Paul Perinbam Introduction
Instruction Set Basic Components
Block Diagrams
Architectural Model,
RTL and Behavioral Model
Test Instructions
Design Complete
18
Dr.Raja
EE141Paul Perinbam Introduction
Design Cycle
19
Dr.Raja
EE141Paul Perinbam Introduction
JOBS IN VLSI
Layout designers
Circuit designers
Architects
Test engineers
Fabrication engineers
System designers
CAD tool programmers
20
Dr.Raja
EE141Paul Perinbam Introduction
VLSI CAD SOCIETIES
ACM SIGDA
Special Interest Group in Design Automation
DATC of IEEE Computer Society
Design Automation Technical Committee
21
Dr.Raja
EE141Paul Perinbam Introduction
VLSI CAD CONFERENCES
DAC
Design Automation Conference
ICCAD
Int’l Conference on Computer-Aided Design
ISPD
Int’l Symposium of Physical Design
ASP-DAC
Asia and South Pacific DAC
DATE
Design Automation and Test in Europe
ISCAS
Int’l Symposium on Circuits and Systems
ICCD
Int’l Conference on Computer Design 22
Dr.Raja
EE141Paul Perinbam Introduction
Moore’s Law
23
Dr.Raja
EE141Paul Perinbam Introduction
Dr.Raja
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
EE141Paul Perinbam
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1959
1960
Moore’s Law
1961
1962
25
Dr.Raja
EE141Paul Perinbam Introduction
Evolution in Complexity
26
Dr.Raja
EE141Paul Perinbam Introduction
Transistor Counts
1 Billion
K Transistors
1,000,000
100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
27
Dr.Raja
EE141Paul Perinbam Courtesy, Intel Introduction
TRANSISTOR SIZE PERSPECTIVE !!!!!
10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
Transistors
0.01 on Lead Microprocessors double every 2 years
8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
29
Dr.Raja
EE141Paul Perinbam Courtesy, Intel Introduction
VLSI Technological Evolution …
thanks to Moore’s Law
30
Dr.Raja
EE141Paul Perinbam Introduction
Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)
P6
100
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years
31
Dr.Raja
EE141Paul Perinbam Courtesy, Intel Introduction
Power Dissipation
100
P6
Pentium ® proc
Power (Watts)
10
486
8086 286
386
8085
1 8080
8008
4004
0.1
1971 1974 1978 1985 1992 2000
Year
32
Dr.Raja
EE141Paul Perinbam Courtesy, Intel Introduction
Power will be a major problem
100000
18KW
10000 5KW
1.5KW
Power (Watts)
1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004
0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year
33
Dr.Raja
EE141Paul Perinbam Courtesy, Intel Introduction
Power density
10000
Rocket
Power Density (W/cm2)
Nozzle
1000
Nuclear
Reactor
100
8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year
34
Dr.Raja
EE141Paul Perinbam Courtesy, Intel Introduction
Not Only Microprocessors
Cell
Phone
Small Power
Signal RF RF
Digital Baseband
(DSP + MCU)
(data from Texas Instruments)
35
Dr.Raja
EE141Paul Perinbam Introduction
Challenges in Digital Design
MODULE
+
GATE
CIRCUIT
DEVICE
G
S D
n+ n+
37
Dr.Raja
EE141Paul Perinbam Introduction
Levels of abstraction
38
Dr.Raja
EE141Paul Perinbam Introduction
LAYERS of an ELECTRONIC PRODUCT
SMART PHONE
System with
Multiple IC’s
Integrated
39
Dr.Raja
EE141Paul Perinbam Introduction
Design Metrics
How to evaluate performance of a
digital circuit (gate, block, …)?
Cost
Reliability
Scalability
Speed (delay, operating frequency)
Power dissipation
Energy to perform a function
40
Dr.Raja
EE141Paul Perinbam Introduction
Cost of Integrated Circuits
NRE (non-recurrent engineering) costs
design time and effort, mask generation
one-time cost factor
Recurrent costs
silicon processing, packaging, test
proportional to volume
proportional to chip area
41
Dr.Raja
EE141Paul Perinbam Introduction
NRE Cost is Increasing
42
Dr.Raja
EE141Paul Perinbam Introduction
Die Cost
Single die
Wafer
From http://www.amd.com 43
Dr.Raja
EE141Paul Perinbam Introduction
Some Examples
Chip Metal Line Wafer Def./ Area Dies/ Yield Die
layers width cost cm2 mm2 wafer cost
386DX 2 0.90 $900 1.0 43 360 71% $4
44
Dr.Raja
EE141Paul Perinbam Introduction
JOBS IN VLSI
Layout designers
Circuit designers
Architects
Test engineers
Fabrication engineers
System designers
CAD tool programmers
Dr.Raja
EE141Paul Perinbam Introduction
VLSI CAD SOCIETIES
ACM SIGDA
Special Interest Group in Design Automation
DATC of IEEE Computer Society
Design Automation Technical Committee
Dr.Raja
EE141Paul Perinbam Introduction
VLSI CAD CONFERENCES
DAC
Design Automation Conference
ICCAD
Int’l Conference on Computer-Aided Design
ISPD
Int’l Symposium of Physical Design
ASP-DAC
Asia and South Pacific DAC
DATE
Design Automation and Test in Europe
ISCAS
Int’l Symposium on Circuits and Systems
ICCD
Int’l Conference on Computer Design
Dr.Raja
EE141Paul Perinbam Introduction
Device for VLSI - NMOS Transistor
Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a
capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal – oxide – semiconductor (MOS)
capacitor
Even though gate is
no longer made of metal
48
Dr.Raja
EE141Paul Perinbam Introduction
Device for VLSI - PMOS Transistor
Source Gate Drain
Polysilicon
SiO2
p+ p+
n bulk Si
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
50
Dr.Raja
EE141Paul Perinbam Introduction
VLSI Basic Building Block - CMOS Inverter
A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF
A Y
GND
51
Dr.Raja
EE141Paul Perinbam Introduction
Inverter Cross-section
Typically use p-type substrate for nMOS
transistors
Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
52
Dr.Raja
EE141Paul Perinbam Introduction
Three-dimensional Integrated
Circuits
Three-dimensional or vertical integration to
boost the performance and extend the
capabilities of modern integrated circuits.
53
Dr.Raja
EE141Paul Perinbam Introduction
Interconnects
Interconnect shielding to
improve signal integrity:
54
Dr.Raja
EE141Paul Perinbam Introduction
Cross section of a JMOS inverter
55
Dr.Raja
EE141Paul Perinbam Introduction
Reduction in wire length
56
Dr.Raja
EE141Paul Perinbam Introduction
A Heterogeneous 3-D System-on-chip
Comprising Sensor and Processing Planes
57
Dr.Raja
EE141Paul Perinbam Introduction
Three-dimensional stacked inverter
58
Dr.Raja
EE141Paul Perinbam Introduction
Various communication schemes for 3-D ICs
59
Dr.Raja
EE141Paul Perinbam Introduction
Challenges for Three-Dimensional Integration
Technological/Manufacturing Limitations
Testing
Interconnect Design
Thermal Issues
CAD Algorithms and Tools
60
Dr.Raja
EE141Paul Perinbam Introduction
Low Power VLSI – Silicon on Insulator
(SOI)
Fundamental physical limits in Bulk-Si devices
towards achieving low power operation:
61
Dr.Raja
EE141Paul Perinbam Introduction
What is SOI?
63
Dr.Raja
EE141Paul Perinbam Introduction
Advantages of SOI
The independent body bias of SOI MOSFETs
makes them faster.
No latch-up.
64
Dr.Raja
EE141Paul Perinbam Introduction
Advantages of SOI
Ideal device isolation and smaller layout area.
SOI devices exhibit excellent radiation hardness
to alpha particles, neutrons and other particles.
Small p-n junction leakage.
65
Dr.Raja
EE141Paul Perinbam Introduction
Power-Aware Testing VLSI
Circuits
Design for Testability (DFT)
To test a given circuit, we need to control and
observe the logic values of internal nodes.
Some nodes in sequential circuits can be
difficult to control and/or observe.
DFT techniques have been proposed to
improve the controllability and observability of
internal nodes.
66
Dr.Raja
EE141Paul Perinbam Introduction
Testing VLSI Circuits……
Observation point insertion
67
Dr.Raja
EE141Paul Perinbam Introduction
Testing VLSI Circuits……
Built-In Self-Test
68
Dr.Raja
EE141Paul Perinbam Introduction
Testing VLSI Circuits……
Test Compression
n<m
69
Dr.Raja
EE141Paul Perinbam Introduction
Thank You
Dr.JRPP
70
Dr.Raja
EE141Paul Perinbam Introduction