8051 Architecture

https://www.youtube.com/watch?v=pA6K5NgWTow
 Features of 8051
• 8 bit ALU.
• 16 bit PC and DPTR.
• 8 bit stack pointer and 8 bit PSW (program status word).
• 4K internal ROM (program memory)
• 128 bytes of Internal RAM.
• four, 8 bit ports P0-P3.
• Two 16 bit timer/counters, T0 & T1.
• Full duplex serial Port.
• Two External and three internal interrupt sources.
• 1.2-12 MHz clock.
• CISC processor
Block Diagram of 8051.
Temp R  R0 to R7
Eg. 10 +20
10 in Acc and 20 in R
ADD A, R4

Register B
Used for multiplication
and Divsion
DIV A,B
MUL A,B

DPTR- 16 bits
Used to access external
memory

SP
PUSH, POP instructions.

Accumulator
Similar to Work register
 Pin details of 8051
P1.0 1 40 Vcc

P1.1 2 39 P0.0(AD0)

P1.2 3 38 P0.1(AD1)

P1.3 4 37 P0.2(AD2)

P1.4 5 36 P0.3(AD3)
Ext
Memory
P1.5 6 8051 35 P0.4(AD4) Address

P1.6 7 34 P0.5(AD5)

P1.7 8 33 P0.6(AD6)

RST 9 32 P0.7(AD7)

(RXD) P3.0 10 31 EA/VPP

(Serial)
Ext Memory
(TXD) P3.1 11 30 ALE/PROG Access Control

(INT0) P3.2 12 29 PSEN

interrupt
(INT1) P3.3 13 28 P2.7(A15)

(T0) P3.4 14 27 P2.6(A14)

Timer
(T1) P3.5 15 26 P2.5(A13)

(WR) P3.6 16 25 P2.4(A12)

Ex M W/R
(RD) P3.7 17 24 P2.3(A11) Ext Memory
Address

XTAL 2 18 23 P2.2(A10)
clock
XTAL 1 19 22 P2.1(A9)

GND 20 21 P2.0(A8)
PROGRAM STATUS WORD (PSW)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CY AC FO RS1 RS0 OV UD P

Symbol Function
CY Carry flag
AC Auxiliary Carry flag, similar to diigit carry
F0 Flag 0 (Available to the user for General Purpose)
Register bank select:
RS1 RS0 Working Register Bank and Address
RS1, 0 0 Bank0 (D:0x00 - D:0x07)
RS0 0 1 Bank1 (D:0x08 - D:0x0F)
1 0 Bank2 (D:0x10 - D:0x17)
1 1 Bank3 (D:0x18H - D:0x1F)
0V Overflow flag
UD User definable flag
P Parity flag – odd parity
 Addressing modes

Immediate Addressing MOV A, #20h – immediate value

Direct Addressing MOV A,30h - address

Indirect Addressing MOV A,@R0 – R0 holds an address

Indexed Addressing MOVC A, @A+DPTR

DPTR has an address + content of Accumulator = source address

of data to be operated
 Internal RAM organization
1F R7
BANK3
7F
18 R0
17 R7

BANK2
10 R0
0F R7

BANK1 2F 7F 78
08 R0

07 R7
BANK0

20 07 00 30
00 R0
Bit Addressible
Hardware Structure of I/O Pin

Read latch Vcc

TB2
Load(L1)

Data bus line D Q P1.X

P1.X pin

Write to latch Clk Q M1

TB1
Read pin
 Writing “1” to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
D Q
1 P1.X
Internal CPU
bus P1.X pin
0 output 1
Write to latch Clk Q M1

TB1
Read pin
 Writing “0” to Output Pin P1.X

Read latch Vcc

TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
D Q
0 P1.X
Internal CPU
bus P1.X pin
1 output 0
Write to latch Clk Q M1

TB1
Read pin
 Reading “High” at Input Pin

Read latch Vcc 1. MOV A,P1

TB2 external pin=High
Load(L1)

1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
2. Read pin=1 Read latch=0
Write to latch=1
 Reading “Low” at Input Pin

Read latch Vcc 1. MOV A,P1

TB2
Load(L1) external pin=Low

0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
2. Read pin=1 Read latch=0
Write to latch=1
Thank you