Subroutines

Subroutines
• Specific task to be executed repeatedly at
different stages of program.
• Similar to the concept of functions in C
 Subroutine process
1. Halt main program, provide returning
2. Transfer control to subroutine
3. Execute subroutine
4. Return back to main program execution.
Continued
Subroutine nesting
Interrupts
 Interrupt Service in PIC
• Several peripherals capable for generating
interrupts.
• PIC has a single interrupt line.
– Interrupt lines from different peripherals and
external interrupts are connected to a single line.
• Each interrupt has  associated interrupt flag
• Global Interrupt Enable (GIE) master control
for interrupts.
 Continued…

External Interrupt

Interrupt line IRQ

Processor IRQ IRQ IRQ IRQ

P1 P2 P3 P4

P – peripheral interrupts ( internal interrupts)

IRQ- interrupt request
Interrupt Process

Similar to subroutine call, when an interrupt is

Encountered

1. Main program halted

2. PC loaded to STACK
3. PC loaded with interrupt vector ( 0x04)
4. Execute ISR
5. Load PC with address from stack
6. Return to main program
 Interrupt Mask
Interrupt flags, eg. T0IF

PIE
Eg. T0IE

PIR- peripheral interrupt Register, PIE- peripheral interrupt enable, T0IF= timer0 interrupt flag
T0IE= timer 0 interrupt enable
 Instructions used
• Returning from Interrupt
– RETFIE
• Return from ISR, with GIE=1
• Widely used
– RETURN
• Normal return from ISR

Note: On detecting an interrupt, the first step in ISR is to

disable GIE (GIE=0) so that during ISR execution , other
interrupts are not detected. Similarly the last step in ISR
will be GIE=1 to detect further interrupts.
IRQ and Response
 Interrupt priority
• All the interrupts have same priority in PIC-
except RESET.
• RESET is non-maskable.
• Priority is assigned while writing ISR.
– Which interrupt flag is to be checked first
 Interrupt priority- example
function ISR( )
{
GIE=0;
If( intA_flag==1) Assuming peripheral A and
{ do …. } peripheral B generated interrupt at
the same time.
if ( intB_flag==1)
{ do…. } In the ISR peripheral A is given high
GIE=1; priority.

}
 Interrupt status saving
• Interrupt may come anytime.
• it is advised to save the contents of Work register and STATUS
register (as the operations in ISR may alter the contents of W
and STATUS)
• Saving the values are done as first steps in ISR, so that these
values could be loaded back once the ISR is completed.
• The saved values could be used and main routine can
continue execution.
• Interrupt status saving should be done by programmer.
 PORTS
General Purpose Input Output (GPIO)
 PORTS
• Most commonly used peripheral.
• Multiplexed functionality ( could be used as GPIO or
for other peripheral functionalities)
• Can be configured as input or as output( any one
configuration at a time)
• Each PORT has multiple lines ( physical pins)
• PORT A, PORT B, PORT C,PORT D,PORT E
• Used for interfacing µC to external world.
Eg. LED, LCD, Switch, Communication, data etc..
 GPIO PIN DIAGRAM

PORTA PORTB

PORTE

PORTD

PORTC
PORTC

PORTD PORTD
 Configuration of GPIO
• TRIS register associated with each PORT.
• TRIS is a Special Function Register(SFR)
• TRIS register control the direction( input or
output) of a PORT.
eg. PORTD has 8 pins -> RD0 to RD7
Each one of these pins could be configured as
input or output.
TRISD 8 bit register
 TRIS register Mapping
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

TRISD

TRISD 0 0 0 0 0 0 0 0

All PORTD pins acting as output

1 1 1 1 1 1 1 1

All PORTD pins acting as input

1 0 0 1 1 1 1 0

RD7, RD4, RD3,RD2,RD1,RD0 input, RD6,RD5 output

 Contd…
• TRIS bit 0 PORT pin in output mode
• TRIS bit 1PORT pin in input mode
• Same logic applicable for all PORTS.
- TRISA, TRISB, TRISC,TRISD, TRISE
• Read and Write operation applicable for PORTS.
• Read operation- PORT pin/pins should be in input
mode .
• Write operation- PORT pin/pins in output mode
 PORTD Block Diagram (single pin)

Buffer

Ref: block diagram from data sheet

 PORT configuration- Output mode
Connected
1 0
1

Data Latch and TRIS Latch are negative edge triggered (high to low)
 PORT Configuration - input mode
Data latch disconnected

0 1 0

Enabled
 PORTB- single pin

L1 - Data latch
L2- TRIS latch
L3- Read Latch
B4- buffer, for signal strength

Ref: block diagram from text book

Output to PORT- waveform

TRIS Latch

Data Latch

F0- phase before port pin configured to be in output mode

F1- port pin in output mode
Data, Tris Latches are negative edge triggered ( high to low)
 RBPU’
• In input mode of operation
• Port pin is given 5V logic ‘1’
• Port pin given 0V  logic ‘0’
• Port pin not at all connected …. ?
Floating state it could be read as ‘1’ or as ‘0’
Solution ?

A weak pull up is provided with PORTB so that all the

pins in input mode will be at logic high state. Depending
on the external circuit the logic will change to low
 Contd…
• RBPU’ ( inverted logic) is the bit controlling
weak pull up feature for PORTB.
• If RBPU’ =0 , then weak pull enabled for ALL
PINS of PORTB.
• As there is only a single RBPU’ bit, weak pull
up cannot be enabled for a single pin of
PORTB.( if enabled all pins have pull up)
• Other ports do not have weak pull up feature.
• RBPU’ bit is in OPTION_REG
 PORTB additional features
1. Interrupt on change
• RB4 to RB7 pins of PORTB has interrupt on
change feature.( only in input mode)
• If configured for this feature, if the logic state
on any of these pins changes from previous
state, an interrupt will be generated.
• this feature could be enabled using RBIE and
RBIF.
• These bits are located inside INTCON register.
 PORTB – Features contd…
External interrupt
• RB0 pin of PORTB could be configured for
external interrupt.
• This feature is enabled by bits in OPTION_REG
and INTCON.
 Registers associated with PORTB
INTCON

GIE= global interrupt enable ( master control for interrupts)

PEIE- master control for peripheral interrupts
INTE= external interrupt enable for RB0
INTF= external interrupt flag
RBIE= interrupt on change enable for RB4-RB7
RBIF= interrupt on change flag.
Registers associated contd…

RBPU’ – weak pull up enable for PORTB

INTEDG - external interrupt edge selection
- 1 interrupt on rising edge of RB0/INT
- 0 interrupt on falling edge of RB0/INT